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參數(shù)資料
| 型號： | AD7840BQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Complete 14-Bit DAC |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 2.5 us SETTLING TIME, 14-BIT DAC, CDIP24 |
| 封裝： | HERMETIC SEALED, CERDIP-24 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 337K |
| 代理商： | AD7840BQ |
AD7840
REV. B
–10–
MICROPROCE SSOR INT E RFACING
T he AD7840 logic architecture allows two interfacing options
for interfacing the part to microprocessor systems. It offers a
14-bit wide parallel format and a serial format. Fast pulse
widths and data setup times allow the AD7840 to interface
directly to most microprocessors including the DSP processors.
Suitable interfaces to various microprocessors are shown in
Figures 15 to 23.
Parallel Interfacing
Figures 15 to 17 show interfaces to the DSP processors, the
ADSP-2100, the T MS32010 and T MS32020. An external
timer controls the updating of the AD7840. Data is loaded to
the AD7840 input latch using the following instructions:
ADSP-2100: DM(DAC) = MR0
T MS32010: OUT DAC,D
T MS32020: OUT DAC,D
MR0 = ADSP-2100 MR0 Register
D = Data Memory Address
DAC = AD7840 Address
Figure 15. AD7840–ADSP-2100 Parallel Interface
Figure 16. AD7840–TMS32010 Parallel Interface
Figure 17. AD7840–TMS32020 Parallel Interface
Some applications may require that the updating of the AD7840
DAC latch be controlled by the microprocessor rather than the
external timer. One option (for double-buffered interfacing) is
to decode the AD7840
LDAC
from the address bus so that a
write operation to the DAC latch (at a separate address than the
input latch) updates the output. An example of this is shown in
the 8086 interface of Figure 18. Note that connecting the
LDAC
input to the
CS
input will not load the DAC latch cor-
rectly since both latches cannot he transparent at the same time.
AD7840–8086 Interface
Figure 18 shows an interface between the AD7840 and the 8086
microprocessor. For this interface, the
LDAC
input is derived
from a decoded address. If the least significant address line, A0,
is decoded then the input latch and the DAC latch can reside at
consecutive addresses. A move instruction loads the input latch
while a second move instruction updates the DAC latch and the
AD7840 output. T he move instruction to load a data word
WX YZ to the input latch is as follows:
MOV DAC,#YZWX
DAC = AD7840 Address
Figure 18. AD7840–8086 Parallel Interface
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