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參數資料
| 型號： | AD7840BQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Complete 14-Bit DAC |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 2.5 us SETTLING TIME, 14-BIT DAC, CDIP24 |
| 封裝： | HERMETIC SEALED, CERDIP-24 |
| 文件頁數： | 7/16頁 |
| 文件大小： | 337K |
| 代理商： | AD7840BQ |
AD7840
REV. B
–7–
T able III. Parallel Mode T ruth T able
CS
WR
LDAC
Function
}
Both Latches Latched
Input Latch T ransparent
Analog Output Updated
Input Latch T ransparent
DAC Latch Data T ransfer Inhibited
Input Latch Is Latched
DAC Latch Data T ransfer Occurs
H
X
L
H
H
X
f
X
H
L
H
X
H
f
H
H
H
L
L
L
L
Input Latch Latched
DAC Latch T ransparent
L
g
g
L
L
X = Don’t Care
Figure 6. Parallel Mode Timing Diagram
Figure 7. AD7840 Simplified Parallel Input Control Logic
Serial Data Format
T he serial data format is selected for the AD7840 by connecting
the
CS
/SERIAL line to –5 V. In this case, the
WR
/
SYNC
,
D13/SDAT A, D12/SCLK , D11/FORMAT and D10/JUST IFY
pins all assume their serial functions. T he unused parallel inputs
should not be left unconnected to avoid noise pickup. Serial
data is loaded to the input latch under control of SCLK ,
SYNC
and SDAT A. T he AD7840 expects a 16-bit stream of serial data
on its SDAT A input. Serial data must be valid on the falling
edge of SCLK . T he
SYNC
input provides the frame synchroni-
zation signal which tells the AD7840 that valid serial data will
be available for the next 16 falling edges of SCLK . Figure 8
shows the timing diagram for serial data format.
Figure 8. Serial Mode Timing Diagram
Although 16 bits of data are clocked into the AD7840, only 14
bits go into the input latch. T herefore, two bits in the stream are
don’t cares since their value does not affect the input latch data.
T he order and position in which the AD7840 accepts the 14 bits
of input data depends upon the FORMAT and JUST IFY in-
puts. T here are four different input data modes which can be
chosen (see T able I in the Pin Function Description section).
T he first mode (M1) assumes that the first two bits of the input
data stream are don’t cares, the third bit is the LSB and the last
(or 16th bit) is the MSB. T his mode is chosen by tying both the
FORMAT and JUST IFY pins to a logic 0. T he second mode
(M2; FORMAT = 0, JUST IFY = 1) assumes that the first bit in
the data stream is the LSB, the fourteenth bit is the MSB and
the last two bits are don’t cares. T he third mode (M3;
FORMAT = 1, JUST IFY 0) assumes that the first two bits in
the stream are again don’t cares, the third bit is now the MSB
and the sixteenth bit is the LSB. T he final mode (M4; FOR-
MAT = 1, JUST IFY= 1) assumes that the first bit is the MSB,
the fourteenth bit is the LSB and the last two bits of the stream
are don’t cares.
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