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參數資料
| 型號： | AD7851ARS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit 333 kSPS Serial A/D Converter |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MO-15AG, SSOP-24 |
| 文件頁數： | 26/36頁 |
| 文件大?。?/td> | 435K |
| 代理商： | AD7851ARS |
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AD7851
–26–
REV. A
MODE 4 and 5 (Self-Clocking Modes)
T he timing diagrams in Figure 38 and Figure 39 are for Inter-
face Modes 4 and 5. Interface Mode 4 has a noncontinuous
SCLK output and Interface Mode 5 has a continuous SCLK
output (SCLK is switched off internally during calibration for
both Modes 4 and 5). T hese modes of operation are especially
different to all the other modes since the SCLK and
SYNC
are
outputs. T he
SYNC
is generated by the part as is the SCLK .
T he master clock at the CLK IN pin is routed directly to the
SCLK pin for Interface Mode 5 (Continuous SCLK ) and the
CLK IN signal is gated with the
SYNC
to give the SCLK
(noncontinuous) for Interface Mode 4.
T he most important point about these two modes of operation
mode is that
the result of the current conversion is clocked out during
the same conversion
and a write to the part during this conversion
is for the next conversion. T he arrangement is shown in Figure
37. Figure 38 and Figure 39 show more detailed timing for the
arrangement of Figure 37.
WRITE N+1
READ N
3.25μs
WRITE N+2
READ N+1
WRITE N+3
READ N+2
THE CONVERSION RESULT DUE TO
WRITE N+1 IS READ HERE
3.25μs
3.25μs
CONVERSION N
CONVERSION N+1
CONVERSION N+2
Figure 37.
In Figure 38 the first point to note is that the BUSY,
SYNC
,
and SCLK are all outputs from the AD7851 with the
CONVST
being the only input signal. Conversion is initiated with the
CONVST
signal going low. T his
CONVST
falling edge also
triggers the BUSY to go high. T he
CONVST
signal rising edge
triggers the
SYNC
to go low after a short delay (2.5 t
CLK IN
to
3.5 t
CLK IN
typically) after which the SCLK will clock out the
data on the DOUT pin during conversion. T he data on the DIN
pin is also clocked in to the AD7851 by the same SCLK for the
next conversion. T he read/write operations must be complete
after sixteen clock cycles (
which takes
3.25
μ
s approximately from
the rising edge of
CONVST
assuming a
6
MHz CLKIN
). At this
time the conversion will be complete, the
SYNC
will go high,
and the BUSY will go low. T he next falling edge of the
CONVST
must occur at least 330 ns after the falling edge of
BUSY to allow the track/hold amplifier adequate acquisition
time as shown in Figure 38. T his gives a throughput time of
3.68
μ
s. T he maximum throughput rate in this case is 272kHz.
t
1
CONVST
(I/P)
SCLK
(O/P)
CONVERSION ENDS
3.25μs LATER
SERIAL READ
AND WRITE
OPERATIONS
OUTPUT SERIAL SHIFT
REGISTER IS RESET
READ OPERATION
SHOULD END 500ns
PRIOR TO NEXT RISING
EDGE OF
CONVST
400ns MIN
BUSY
(O/P)
SYNC
(O/P)
CONVERSION IS INITIATED
AND TRACK/HOLD GOES
INTO HOLD
t
1
= 100ns MIN
t
CONVERT
= 3.25μs
Figure 38. Mode 4, 5 Timing Diagram (SM1 = 1, SM2 = 1
and 0)
In these interface modes the part is now the master and the
DSP is the slave. Figure 39 is an expansion of Figure 38. T he
AD7851 will ensure
SYNC
goes low after the rising edge C of
the continuous SCLK (Interface Mode 5) in Figure 39. Only in
the case of a noncontinuous SCL K (Interface Mode 4) will
the time t
4
apply. T he first data bit is clocked out from the
falling edge of
SYNC
. T he SCL K rising edge clocks out all
subsequent bits on the DOUT pin. T he input data present on
the DIN pin is clocked in on the rising edge of the SCLK . T he
POLARIT Y pin may be used to change the SCLK edge which
the data is sampled on and clocked out on. T he
SYNC
will go
high after the 16th SCLK rising edge and before the rising edge
D of the continuous SCLK in Figure 39. T his ensures the part
will not clock in an extra bit from the DIN pin or clock out an
DB12
DB0
DB10
DB11
DB13
DB14
DB15
DB0
DB10
DB12
DB13
DB14
DB15
DB11
3-STATE
3-STATE
POLARITY PIN
LOGIC HIGH
SYNC
(O/P)
1
6
2
3
4
5
16
SCLK (O/P)
t
9
t
5
t
11A
t
4
t
10
t
12
DOUT (O/P)
t
8
DIN (I/P)
t
4
= 0.6 t
SCLK
(NONCONTINUOUS SCLK), t
6
= 45ns MAX,
t
7
= 30ns
MIN, t
8
= 20ns
MIN , t
11A
= 50ns MAX
t
6
t
7
t
8
D
C
Figure 39. Timing Diagram for Read/Write with
SYNC
Output and SCLK Output (Continuous and Noncontinuous)
(i.e., Operating Mode Numbers 4 and 5, SM1 = 1, SM2 = 1 and 0)
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