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參數資料
| 型號： | AD7853AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數： | 14/34頁 |
| 文件大小： | 350K |
| 代理商： | AD7853AR |
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REV. B
–14–
AD7853/AD7853L
edge of
CONVST
occurs at least 10 ns typically before this
CLKIN edge. The conversion cycle will take 16.5 CLKIN
periods from this CLKIN falling edge. If the 10 ns setup time is
not met, the conversion will take 17.5 CLKIN periods. The
maximum specified conversion time is 4.6
μ
s for the AD7853
(18 t
CLKIN,
CLKIN = 4 MHz) and 10
μ
s for the AD7853L (18
t
CLKIN
, CLKIN = 1.8 MHz). When a conversion is completed,
the BUSY output goes low, and then the result of the conver-
sion can be read by accessing the data through the serial inter-
face. To obtain optimum performance from the part, the read
operation should not occur during the conversion or 400ns
prior to the next
CONVST
rising edge. However, the maximum
throughput rates are achieved by reading/writing during conver-
sion, and reading/writing during conversion is likely to degrade
the Signal to (Noise + Distortion) by only 0.5 dBs. The AD7853
can operate at throughput rates up to 200 kHz, 100 kHz for
the AD7853L. For the AD7853/AD7853L a conversion takes
18 CLKIN periods, 2 CLKIN periods are needed for the
acquisition time giving a full cycle time of 5
μ
s (= 200 kHz,
CLKIN = 4 MHz). For the AD7853L 100 kHz throughput can
be obtained as follows: the CLKIN and
CONVST
signals are
arranged to give a conversion time of 16.5 CLKIN periods as
described above, 1.5 CLKIN periods are allowed for the acqui-
sition time. This gives a full cycle time of 10
μ
s (= 100 kHz,
CLKIN = 1.8 MHz). When using the software conversion start
for maximum throughput, the user must ensure the control register
write operation extends beyond the falling edge of BUSY. The
falling edge of BUSY resets the
CONVST
bit to 0 and allows it to
be reprogrammed to 1 to start the next conversion.
CIRCUIT INFORMATION
The AD7853/AD7853L is a fast, 12-bit single supply A/D con-
verter. The part requires an external 4 MHz/1.8 MHz master
clock (CLKIN), two C
REF
capacitors, a
CONVST
signal to start
conversion and power supply decoupling capacitors. The part
provides the user with track/hold, on-chip reference, calibration
features, A/D converter and serial interface logic functions on a
single chip. The A/D converter section of the AD7853/AD7853L
consists of a conventional successive-approximation converter
based around a capacitor DAC. The AD7853/AD7853L accepts
an analog input range of 0 to +V
DD
where the reference can be
tied to V
DD
. The reference input to the part is buffered on-chip.
A major advantage of the AD7853/AD7853L is that a conver-
sion can be initiated in software as well as applying a signal to
the
CONVST
pin. Another innovative feature of the AD7853/
AD7853L is self-calibration on power-up, which is initiated
having a capacitor from the
CAL
pin to AGND, to give superior
dc accuracy (See Automatic Calibration on Power-Up section).
The part is available in a 24-lead SSOP package, which offers
the user considerable space-saving advantages over alternative
solutions. The AD7853L version typically consumes only 5.5mW,
making it ideal for battery-powered applications.
CONVERTER DETAILS
The master clock for the part must be applied to the CLKIN
pin. Conversion is initiated on the AD7853/AD7853L by puls-
ing the
CONVST
input or by writing to the control register and
setting the
CONVST
bit to 1. On the rising edge of
CONVST
(or at the end of the control register write operation), the on-
chip track/hold goes from track to hold mode. The falling edge
of the CLKIN signal which follows the rising edge of the edge of
CONVST
signal initiates the conversion, provided the rising
AV
DD
DV
DD
AIN(+)
AIN(–)
AMODE
C
REF1
C
REF2
SLEEP
DIN
DOUT
SYNC
SM1
SM2
CONVST
AGND
DGND
CLKIN
SCLK
REF
IN
/REF
OUT
POLARITY
CAL
AD7853/53L
ANALOG SUPPLY
+3V TO +5V
0.1
m
F
0.1
m
F
10
m
F
DV
DD
UNIPOLAR
RANGE
0.1
m
F
0.01
m
F
SERIAL MODE
SELECTION BITS
MASTER CLOCK INPUT
CONVERSION
START INPUT
FRAME SYNC OUTPUT
SERIAL DATA OUTPUT
0.1
m
F
AUTO CAL ON
POWER-UP
INTERNAL/EXTERNAL
REFERENCE
0V TO 2.5V
INPUT
4MHz/1.8MHz OSCILLATOR
SERIAL CLOCK OUTPUT
DV
DD
200kHz/100kHz PULSE
GENERATOR
CH1
CH2
CH3
CH4
OSCILLOSCOPE
OPTIONAL EXTERNAL
REFERENCE
AD780/REF-192
DIN AT DGND
=> NO WRITING
TO DEVICE
0.01
m
F
4 LEADING ZEROS
FOR ADC DATA
Figure 10. Typical Circuit
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