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參數資料
| 型號： | AD7853L* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single Supply V.35 Transceiver; Package: SO; No of Pins: 28; Temperature Range: -40°C to +85°C |
| 中文描述： | 3 V至5 V單電源。 200 kSPS的12位采樣ADC |
| 文件頁數： | 18/34頁 |
| 文件大小： | 350K |
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REV. B
–18–
AD7853/AD7853L
is powered down and I
DD
is 400
μ
A typ. The choice of full or par-
tial power-down does not give any significant improvement in
throughput with a power-down between conversions. This is
discussed in the next section–Power-Up Times. However, a
partial power-down does allow the on-chip reference to be used
externally even though the rest of the AD7853 circuitry is pow-
ered down. It also allows the AD7853 to be powered up faster
after a long power-down period when using the on-chip refer-
ence (See Power-Up Times–Using On-Chip Reference).
When using the
SLEEP
pin, the power management bits PMGT1
and PMGT0 should be set to zero (default status on power-up).
Bringing the
SLEEP
pin logic high ensures normal operation,
and the part does not power down at any stage. This may be
necessary if the part is being used at high throughput rates when
it is not possible to power down between conversions. If the user
wishes to power down between conversions at lower throughput
rates (i.e. <100 kSPS for the AD7853) to achieve better power
performances, then the
SLEEP
pin should be tied logic low.
If the power-down options are to be selected in software only,
then the
SLEEP
pin should be tied logic high. By setting the
power management bits PMGT1 and PMGT0 as shown in
Table VI, a Full Power-Down, Full Power-Up, Full Power-
Down Between Conversions, and a Partial Power-Down Be-
tween Conversions can be selected.
A typical connection diagram for a low power application is
shown in Figure 23 (AD7853L is the low power version of the
AD7853).
INPUT FREQUENCY – kHz
Figure 22. PSRR vs. Frequency
–78
–80
–90
0
100
P
20
40
60
80
–82
–84
–86
5.0V
3.3V
AV
= DV
= 3.3V/5.0V,
100mV p-p SINE WAVE ON AV
DD
–88
POWER-DOWN OPTIONS
The AD7853 provides flexible power management to allow the
user to achieve the best power performance for a given through-
put rate. The power management options are selected by
programming the power management bits, PMGT1 and PMGT0,
in the control register and by use of the
SLEEP
pin. Table VI
summarizes the power-down options that are available and how
they can be selected by using either software, hardware or a
combination of both. The AD7853 can be fully or partially
powered down. When fully powered down, all the on-chip cir-
cuitry is powered down and I
DD
is 1
μ
A typ. If a partial power-
down is selected, then all the on-chip circuitry except the reference
AV
DD
DV
DD
AIN(+)
AIN(–)
AMODE
C
REF1
C
REF2
SLEEP
DIN
DOUT
SYNC
SM1
SM2
CONVST
AGND
DGND
CLKIN
SCLK
REF
IN
/REF
OUT
POLARITY
CAL
AD7853L
0.1
m
F
0.1
m
F
10
m
F
DV
DD
UNIPOLAR RANGE
0.1
m
F
0.01
m
F
SERIAL MODE
SELECTION BITS
MASTER CLOCK INPUT
CONVERSION
START INPUT
SERIAL DATA OUTPUT
0.1
m
F
0.01
m
F
INTERNAL
REFERENCE
0V TO 2.5V
INPUT
1.8MHz OSCILLATOR
SERIAL CLOCK INPUT
100kHz PULSE
GENERATOR
DIN AT DGND
=> NO WRITING
TO DEVICE
AUTO POWER-
DOWN AFTER
CONVERSION
THREE-WIRE
MODE
SELECTED
LOW POWER
m
C/
m
P
AUTO CAL ON
POWER-UP
CURRENT, I = 1.5mA TYP
REF-192
ANALOG SUPPLY
+3V
OPTIONAL EXTERNAL
REFERENCE
Figure 23. Typical Low Power Circuit
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相關代理商/技術參數 |
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| AD7853LAN | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 12-bit Serial 24-Pin PDIP 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 12-BIT SERL 24PDIP - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:SELF CAL. SERIAL 12 BIT ADC I.C. - Bulk 制造商:Analog Devices 功能描述:IC 12BIT ADC 7853 DIP24 制造商:Analog Devices 功能描述:3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| AD7853LANZ | 功能描述:IC ADC 12BIT SRL 200KSPS 24-DIP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
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