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參數(shù)資料
| 型號(hào)： | AD7853L* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single Supply V.35 Transceiver; Package: SO; No of Pins: 28; Temperature Range: -40°C to +85°C |
| 中文描述： | 3 V至5 V單電源。 200 kSPS的12位采樣ADC |
| 文件頁(yè)數(shù)： | 7/34頁(yè) |
| 文件大小： | 350K |
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REV. B
–7–
AD7853/AD7853L
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Description
1
CONVST
Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode and
starts conversion. When this input is not used, it should be tied to DV
DD
.
Busy Output. The busy output is triggered high by the falling edge of
CONVST
or rising edge of
CAL
, and
remains high until conversion is completed. BUSY is also used to indicate when the AD7853/AD7853L has
completed its on-chip calibration sequence.
Sleep Input/Low Power Mode. A Logic 0 initiates a sleep and all circuitry is powered down including the
internal voltage reference provided there is no conversion or calibration being performed. Calibration data
is retained. A Logic 1 results in normal operation. See Power-Down section for more details.
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this appears
at the pin. This pin can be overdriven by an external reference or can be taken as high as AV
DD
. When this
pin is tied to AV
DD
, or when an externally applied reference approaches AV
DD
, the C
REF1
pin should also be
tied to AV
DD
.
Analog Positive Supply Voltage, +3.0 V to +5.5 V.
Analog Ground. Ground reference for track/hold, reference and DAC.
Reference Capacitor (0.1
μ
F multilayer ceramic). This external capacitor is used as a charge source for the
internal DAC. The capacitor should be tied between the pin and AGND.
Reference Capacitor (0.01
μ
F ceramic disc). This external capacitor is used in conjunction with the on-chip
reference. The capacitor should be tied between the pin and AGND.
Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above
AV
DD
at any time, and cannot go below AIN(–) when the unipolar input range is selected.
Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above
AV
DD
at any time.
No Connect Pin.
Analog Mode Pin. This pin allows two different analog input ranges to be selected. A Logic 0 selects range
0 to V
REF
(i.e., AIN(+) – AIN(–) = 0 to V
REF
). In this case AIN(+) cannot go below AIN(–) and
AIN(–) cannot go below AGND. A Logic 1 selects range –V
REF
/2 to +V
REF
/2 (i.e., AIN(+) – AIN(–) =
–V
REF
/2 to +V
REF
/2). In this case AIN(+) cannot go below AGND so that AIN(–) needs to be biased to
+V
REF
/2 to allow AIN(+) to go from 0 V to +V
REF
V.
Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will
reverse the active edge of the serial clock (SCLK). A Logic 1 means that the serial clock (SCLK) idles high
and a Logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and
Table IX for the SCLK active edges.
Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of opera-
tion as described in Table X.
Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of opera-
tion as described in Table X.
Calibration Input. This pin has an internal pull-up current source of 0.15
μ
A. A Logic 0 on this pin resets
all calibration control logic and initiates a calibration on its rising edge. There is the option of connecting a
10 nF capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This input
overrides all other internal operations. If the autocalibration is not required, this pin should be tied to a
logic high.
Digital Supply Voltage, +3.0 V to +5.5 V.
Digital Ground. Ground reference point for digital circuitry.
Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.
Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act
as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table X).
Master Clock Signal for the device (4 MHz for AD7853, 1.8 MHz for AD7853L). Sets the conversion and
calibration times.
Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the
type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and
SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin.
This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync
in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table X).
2
BUSY
3
SLEEP
4
REF
IN
/
REF
OUT
5
6, 12 AGND
7
C
REF1
AV
DD
8
C
REF2
9
AIN(+)
10
AIN(–)
11
13
NC
AMODE
14
POLARITY
15
SM1
16
SM2
17
CAL
18
19
20
21
DV
DD
DGND
DOUT
DIN
22
CLKIN
23
SCLK
24
SYNC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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| AD7853LANZ | 功能描述:IC ADC 12BIT SRL 200KSPS 24-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7853LAR | 功能描述:IC ADC 12BIT SRL 200KSPS 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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