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參數資料
| 型號： | AD7858LAR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
| 中文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數： | 15/32頁 |
| 文件大小： | 315K |
| 代理商： | AD7858LAR |
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AD7858/AD7858L
REV. B
–15–
CIRCUIT INFORMATION
The AD7858/AD7858L is a fast, 12-bit single supply A/D con-
verter. The part requires an external 4 MHz/1.8 MHz master
clock (CLKIN), two C
REF
capacitors, a
CONVST
signal to start
conversion, and power supply decoupling capacitors. The part
provides the user with track/hold, on-chip reference, calibration
features, A/D converter, and serial interface logic functions on a
single chip. The A/D converter section of the AD7858/AD7858L
consists of a conventional successive-approximation converter
based around a capacitor DAC. The AD7858/AD7858L accepts
an analog input range of 0 to +V
DD
where the reference can be
tied to V
DD
. The reference input to the part is buffered on-chip.
A major advantage of the AD7858/AD7858L is that a conversion
can be initiated in software as well as applying a signal to the
CONVST
pin. Another innovative feature of the AD7858/
AD7858L is self-calibration on power-up, which is initiated
having a capacitor from the
CAL
pin to AGND, to give superior
dc accuracy. See Automatic Calibration on Power-Up section.
The part is available in a 24-pin SSOP package and this offers
the user considerable space-saving advantages over alternative
solutions. The AD7858L version typically consumes only
5.5 mW making it ideal for battery-powered applications.
CONVERTER DETAILS
The master clock for the part must be applied to the CLKIN
pin. Conversion is initiated on the AD7858/AD7858L by pulsing
the
CONVST
input or by writing to the control register and
setting the CONVST bit to 1. On the rising edge of
CONVST
(or at the end of the control register write operation), the on-
chip track/hold goes from track to hold mode. The falling edge
of the CLKIN signal that follows the rising edge of the
CONVST
signal initiates the conversion, provided the rising edge of
CONVST
occurs at least 10 ns typically before this CLKIN
edge. The conversion cycle will take 16.5 CLKIN periods from
this CLKIN falling edge. If the 10 ns setup time is not met, the
conversion will take 17.5 CLKIN periods. The maximum speci-
fied conversion time is 4.6
μ
s for the AD7858 (18t
CLKIN
,
CLKIN = 4 MHz) and 10
μ
s for the AD7858L (18t
CLKIN
,
CLKIN = 1.8 MHz). When a conversion is completed, the
BUSY output goes low, and then the result of the conversion
can be read by accessing the data through the serial interface.
To obtain optimum performance from the part, the read opera-
tion should not occur during the conversion or 400 ns prior to
the next
CONVST
rising edge. However, the maximum
throughput rates are achieved by reading/writing during conver-
sion, and reading/writing during conversion is likely to degrade
the Signal to (Noise + Distortion) by only 0.5 dBs. The AD7858
can operate at throughput rates up to 200 kHz, 100 kHz for the
AD7858L. For the AD7858 a conversion takes 18 CLKIN
periods; 2 CLKIN periods are needed for the acquisition time
giving a full cycle time of 5
μ
s (= 200 kHz, CLKIN = 4 MHz).
For the AD7858L 100 kHz throughput can be obtained as
follows: the CLKIN and
CONVST
signals are arranged to give
a conversion time of 16.5 CLKIN periods as described above,
1.5 CLKIN periods are allowed for the acquisition time. This
gives a full cycle time of 10
μ
s (=100 kHz, CLKIN = 1.8 MHz).
When using the software conversion start for maximum through-
put the user must ensure the control register write operation
extends beyond the falling edge of BUSY. The falling edge of
BUSY resets the
CONVST
bit to 0 and allows it to be repro-
grammed to 1 to start the next conversion.
TYPICAL CONNECTION DIAGRAM
Figure 10 shows a typical connection diagram for the AD7858/
AD7858L. The AGND and the DGND pins are connected
together at the device for good noise suppression. The
CAL
pin
has a 0.01
μ
F capacitor to enable an automatic self-calibration
on power-up. The conversion result is output in a 16-bit word
with four leading zeros followed by the MSB of the 12-bit result.
Note that after the AV
DD
and DV
DD
power-up the part will
CH1
CH2
CH3
CH4
CH5
OSCILLOSCOPE
4 LEADING
ZEROS FOR
ADC DATA
AUTO CAL ON
POWER-UP
OPTIONAL
EXTERNAL
REFERENCE
AD780/
REF-192
4MHz/1.8MHz OSCILLATOR
MASTER CLOCK
INPUT
0.1 F
0.1 F
10 F
ANALOG SUPPLY
+3V TO +5V
0V TO 2.5V
INPUT
0.1 F
0.01 F
DV
DD
0.01 F
0.1 F
INTERNAL/
EXTERNAL
REFERENCE
200kHz/100kHz PULSE GENERATOR
CONVERSION
START INPUT
SERIAL CLOCK
INPUT
FRAME SYNC INPUT
SERIAL DATA INPUT
SERIAL DATA
OUTPUT
DATA GENERATOR
PULSE GENERATOR
CLKIN
SCLK
CONVST
SYNC
DIN
DOUT
DGND
AGND
CAL
SLEEP
C
REF2
C
REF1
AIN(–)
AIN(+)
AV
DD
DV
DD
AD7858/
AD7858L
Figure 10. Typical Circuit
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7858LAR3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
| AD7858LAR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 12-bit Serial 24-Pin SOIC W T/R |
| AD7858LARS | 功能描述:IC ADC 12BIT 8CH SRL 24-SSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7858LARS3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
| AD7858LARS-REEL | 功能描述:IC ADC 12BIT 8CH SRL 24-SSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
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