- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373920 > AD7858LAR (ANALOG DEVICES INC) 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC PDF資料下載
參數(shù)資料
| 型號(hào)： | AD7858LAR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
| 中文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 4/32頁 |
| 文件大小： | 315K |
| 代理商： | AD7858LAR |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
REV. B
–4–
AD7858/AD7858L
TIMING SPECIFICATIONS
1
(AV
DD
= DV
DD
= +3.0 V to +5.5 V; f
CLKIN
= 4 MHz for AD7858 and 1.8/1 MHz for AD7858L;
T
A
= T
MIN
to T
MAX
, unless otherwise noted)
5 V
Limit at T
MIN
, T
MAX
(A, B Versions)
Parameter
f
CLKIN2
3 V
Units
Description
500
4
1.8
1
4
100
50
4.6
10 (18)
–0.4 t
SCLK
0.4 t
SCLK
50
50
75
40
20
0.4 t
SCLK
0.4 t
SCLK
30
30/0.4 t
SCLK
50
90
50
2.5 t
CLKIN
2.5 t
CLKIN
31.25
500
4
1.8
1
4
100
90
4.6
10 (18)
–0.4 t
SCLK
0.4 t
SCLK
90
90
115
60
30
0.4 t
SCLK
0.4 t
SCLK
50
50/0.4 t
SCLK
50
130
90
2.5 t
CLKIN
2.5 t
CLKIN
31.25
kHz min
MHz max
MHz max
MHz max
MHz max
ns min
ns max
μ
s max
μ
s max
ns min
ns min/max
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns max
ns max
ns max
ns max
ms typ
Master Clock Frequency
L Version, 0
°
C to +70
°
C, B Grade Only
L Version, –40
°
C to +85
°
C
f
SCLK
t
13
t
2
t
CONVERT
CONVST
Pulsewidth
CONVST
↓
to BUSY
↑
Propagation Delay
Conversion Time = 18 t
CLKIN
L Version 1.8 (1) MHz CLKIN. Conversion Time = 18 t
CLKIN
SYNC
↓
to SCLK
↓
Setup Time (Noncontinuous SCLK Input)
SYNC
↓
to SCLK
↓
Setup Time (Continuous SCLK Input)
Delay from
SYNC
↓
Until DOUT Three-State Disabled
Delay from
SYNC
↓
Until DIN Three-State Disabled
Data Access Time After SCLK
↓
Data Setup Time Prior to SCLK
↑
Data Valid to SCLK Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK
↑
to
SYNC
↑
Hold Time (Noncontinuous SCLK)
(Continuous SCLK)
Delay from
SYNC
↑
Until DOUT Three-State Enabled
Delay from SCLK
↑
to DIN Being Configured as Output
Delay from SCLK
↑
to DIN Being Configured as Input
CAL
↑
to BUSY
↑
Delay
CONVST
↓
to BUSY
↑
Delay in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent
(125013 t
CLKIN
)
Internal DAC Plus System Full-Scale Calibration Time, Master
Clock Dependent (111114 t
CLKIN
)
System Offset Calibration Time, Master Clock Dependent
(13899 t
CLKIN
)
t
3
t
44
t
54
t
64
t
7
t
8
t
9
t
10
t
11
t
125
t
13
t
146
t
15
t
16
t
CAL7
t
CAL17
27.78
27.78
ms typ
t
CAL27
3.47
3.47
ms typ
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
See Table XI and timing diagrams for different interface modes and Calibration.
2
Mark/Space ratio for the master clock input is 40/60 to 60/40.
3
The
CONVST
pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different
CONVST
pulsewidth will apply
(see Power-Down section).
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5
t
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
12
, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
6
t
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the
true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.
7
The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8/1 MHz master clock.
Specifications subject to change without notice.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7858LBN | 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
| AD7858LBR | 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
| AD7858L* | 3 V to 5 V Single Supply. 200 kSPS 8-Channel. 12-Bit Sampling ADC |
| AD7862AR-2 | Simultaneous Sampling Dual 250 kSPS 12-Bit ADC |
| AD7862SQ-10 | Simultaneous Sampling Dual 250 kSPS 12-Bit ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7858LAR3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
| AD7858LAR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 12-bit Serial 24-Pin SOIC W T/R |
| AD7858LARS | 功能描述:IC ADC 12BIT 8CH SRL 24-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7858LARS3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
| AD7858LARS-REEL | 功能描述:IC ADC 12BIT 8CH SRL 24-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。