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參數(shù)資料
| 型號(hào)： | AD7862SQ-10 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Simultaneous Sampling Dual 250 kSPS 12-Bit ADC |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | CERDIP-28 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大小： | 414K |
| 代理商： | AD7862SQ-10 |
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AD7862
TIMING CHARACTERISTICS
1, 2
–4–
REV. 0
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7862 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
A, B
Versions
S
Version
Parameter
Units
Test Conditions/Comments
t
CONV
t
ACQ
Parallel Interface
t
1
t
2
t
3
t
4
t
53
3.6
0.3
3.6
0.3
μ
s max
us max
Conversion Time
Acquisition Time
0
0
35
35
12
60
5
30
40
0
0
45
45
12
70
5
40
40
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
CS
to
RD
Setup Time
CS
to
RD
Hold Time
CONVST
Pulse Width
Read Pulse Width
Data Access Time After Falling Edge of
RD
t
64
Bus Relinquish Time After Rising Edge of
RD
t
7
Time Between Consecutive Reads
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.
2
See Figure 1.
3
Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
(V
DD
= +5 V
6
5%, AGND = DGND = 0 V, REF = Internal. All Specifications T
MIN
to T
MAX
unless
otherwise noted.)
V
A1
V
A2
V
B1
V
B2
t
3
t
1
t
2
t
4
t
5
t
6
t
CONV
t
7
CONVST
BUSY
A0
CS
RD
DATA
.........
.........
Figure 1. Timing Diagram
+1.6V
1.6mA
200μA
50pF
TO
OUTPUT
PIN
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
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