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參數資料
| 型號： | AD7864AS-2 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC |
| 中文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | PLASTIC, MO-112-AA, MQFP-44 |
| 文件頁數： | 17/19頁 |
| 文件大小： | 214K |
| 代理商： | AD7864AS-2 |
AD7864
–17–
REV. A
MICROPROCESSOR INTERFACING
The high speed parallel interface of the AD7864 allows easy
interfacing to most DSP processors and microprocessors.
The ADC7864 interface of the AD7864 consists of the data
lines (DB0–DB11),
CS
,
RD
,
WR
,
EOC
and BUSY.
AD7864–ADSP-2100/ADSP-2101/ADSP-2102 Interface
Figure 20 shows an interface between the AD7864 and the
ADSP-2100. The
CONVST
signal can be generated by the
ADSP-2100 or from some other external source. Figure 20
shows the
CS
being generated by a combination of the
DMS
signal and the address bus of the ADSP-2100. In this way
the AD7864 is mapped into the data memory space of the
ADSP-2100.
The AD7864 BUSY line provides an interrupt to the ADSP-
2100 when the conversion sequence is complete on all the
selected channels. The conversion results can then be read from
the AD7864 using successive read operations. Alternately, one
can use the
EOC
pulse to interrupt the ADSP-2100 when the
conversion on each channel is complete when reading between
each conversion in the conversion sequence (Figure 7). The
AD7864 is read using the following instruction
MR0 = DM(ADC)
where MR0 is the ADSP-2100 MR0 register and ADC is the
AD7864 address.
CS
RD
WR
BUSY
CONVST
DB0–DB11
AD7864
V
IN1
V
IN2
V
IN3
V
IN4
DT1/F0
IRQn
RD
WR
D0–D24
DMS
A0–A13
ADSP-2100/1/2
ADDRESS
DECODE
Figure 20. AD7864–ADSP-2100 Interface
AD7864–TMS320C5x Interface
Figure 21 shows an interface between the AD7864 and the
TMS320C5x. As with the previous interfaces, conversion can be
initiated from the TMS320C5x or from an external source and
the processor is interrupted when the conversion sequence is
completed. The
CS
signal to the AD7864 is derived from the
DS signal and a decode of the address bus. This maps the AD7864
into external data memory. The
RD
signal from the TMS320 is
used to enable the ADC data onto the data bus. The AD7864
has a fast parallel bus so there are no wait state requirements.
The following instruction is used to read the conversion results
from the AD7864:
IN D,ADC
where D is Data Memory address and ADC is the AD7864
address.
CS
RD
WR
BUSY
CONVST
DB0–DB11
AD7864
V
IN1
V
IN2
V
IN3
V
IN4
PA0
INTn
RD
WE
D0–D15
DS
A0–A13
TMS320C5x
ADDRESS
DECODE
Figure 21. AD7864–TMS320C5x Interface
AD7864–MC68000 Interface
An interface between the AD7864 and the MC68000 is shown
in Figure 22. The conversion can be initiated from the MC68000
or from an external source. The AD7864 BUSY line can be
used to interrupt the processor or, alternatively, software delays
can ensure that conversion has been completed before a read to
the AD7864 is attempted. Because of the nature of its inter-
rupts, the 68000 requires additional logic (not shown in Figure
22) to allow it to be interrupted correctly. For further informa-
tion on 68000 interrupts, consult the 68000 Users Manual.
The MC68000
AS
and R/
W
outputs are used to generate a
separate
RD
input signal for the AD7864.
RD
is used to drive
the 68000
DTACK
input to allow the processor to execute a
normal read operation to the AD7864. The conversion results
are read using the following 68000 instruction:
MOVE.W ADC,D0
where D0 is the 68000 D0 register and ADC is the AD7864
address.
CS
RD
CONVST
DB0–DB11
AD7864
V
IN1
V
IN2
V
IN3
V
IN4
DTACK
AS
D0–D15
A0–A15
MC68000
ADDRESS
DECODE
CLOCK
R/
W
Figure 22. AD7864–MC68000 Interface
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| AD7864AS-2Z | 制造商:Analog Devices 功能描述:ADC 12BIT 4CH 500KSPS 44MQ 制造商:Analog Devices 功能描述:ADC, 12BIT, 4CH, 500KSPS, 44MQFP; Resolution (Bits):12bit; Sampling Rate:520kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Supply Current:24mA; Digital IC Case Style:MQFP; No. of Pins:44; Input ;RoHS Compliant: Yes |
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| AD7864AS-3REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 520ksps 12-bit Parallel 44-Pin MQFP T/R |
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