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參數(shù)資料
| 型號： | AD7865BS-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Four-Channel, Simultaneous Sampling, Fast, 14-Bit ADC |
| 中文描述： | 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大小： | 195K |
| 代理商： | AD7865BS-3 |
AD7865
–15–
REV. A
When operating the AD7865 in a standby mode between con-
versions, the power savings can be significant. For example,
with a throughput rate of 10 kSPS and external reference, the
AD7865 will be powered up 11
μ
s out of every 100
μ
s (1
μ
s for
wake-up time and 9.6
μ
s to convert four channels. Therefore,
the average power consumption drops to (115 mW
×
10.6%) or
12.2 mW approximately.
OFFSET AND FULL-SCALE ADJUSTMENT
In most Digital Signal Processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Invariably, some applications will require
that the input signal span the full analog input dynamic range.
In such applications, offset and full-scale error will have to be
adjusted to zero.
Figure 13 shows a typical circuit that can be used to adjust the
offset and full-scale errors on the AD7865 (V
1
on the AD7865-1
version is shown for example purposes only). Where adjustment
is required, offset error must be adjusted before full-scale error.
This is achieved by trimming the offset of the op amp driving
the analog input of the AD7865 while the input voltage is
1/2 LSB below analog ground. The trim procedure is as follows:
apply a voltage of –610
μ
V (–1/2 LSB) at V
1
and adjust the op
amp offset voltage until the ADC output code flickers between
1111 1111 1111 and 0000 0000 0000.
Gain error can be adjusted at either the first code transition
(ADC negative full scale) or the last code transition (ADC posi-
tive full scale). The trim procedures for both cases are as follows.
V
1
R1
10k
V
R2
500
V
R3
10k
V
AGND
AD7865*
*ADDITIONAL PINS OMITTED FOR CLARITY
INPUT
RANGE =
6
10V
R5
10k
V
V
INxA
R4
10k
V
Figure 13. Full-Scale Adjust Circuit
Positive Full-Scale Adjust
Apply a voltage of +9.9982 V (FS/2 – 3/2 LSB) at V
1
. Adjust R2
until the ADC output code flickers between 01 1111 1111 1110
and 01 1111 1111 1111.
Negative Full-Scale Adjust
Apply a voltage of –9.9998 V (–FS + 1/2 LSB) at V
1
and adjust
R2 until the ADC output code flickers between 10 0000 0000
0000 and 10 0000 0000 0001.
An alternative scheme for adjusting full-scale error in systems
that use an external reference is to adjust the voltage at the V
REF
pin until the full-scale error for any of the channels is adjusted
out. The good full-scale matching of the channels will ensure
small full-scale errors on the other channels.
DYNAMIC SPECIFICATIONS
The AD7865 is specified and 100% tested for dynamic perfor-
mance specifications as well as traditional dc specifications such
as Integral and Differential Nonlinearity. These ac specifications
are required for such signal processing applications as phased array
sonar, adaptive filters and spectrum analysis. These applications
require information on the ADC’s effect on the spectral content
of the input signal. Hence, the parameters for which the AD7865
is specified include SNR, harmonic distortion, intermodulation
distortion and peak harmonics. These terms are discussed in
more detail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (f
S
/2) excluding dc. SNR is depen-
dent upon the number of quantization levels used in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal to noise ratio for a sine wave input
is given by
SNR
= (6.02
N
+ 1.76)
dB
where
N
is the number of bits.
Thus for an ideal 14-bit converter, SNR = 86.04 dB.
Figure 14 shows a histogram plot for 8192 conversions of a dc
input using the AD7865 with 5 V supply. The analog input was
set at the center of a code transition. It can be seen that most of
the codes appear in the one output bin, indicating very good
noise performance from the ADC.
(1)
CONVST
BUSY
STBY
100
m
s
I
DD
= 3
m
A
t
BUSY
t
WAKEUP
t
BUSY
7
m
s
Figure 12. Power-Down Between Conversion Sequences
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7865BS-3REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP T/R |
| AD7865BSZ-1 | 功能描述:IC ADC 14BIT 4CHAN 5V 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7865BSZ-1 | 制造商:Analog Devices 功能描述:ADC, 14BIT, 100KSPS, PARALLEL, QFP-44 |
| AD7865BSZ-1REEL | 功能描述:IC ADC 14BIT 4CHAN 5V 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7865BSZ-2 | 功能描述:IC ADC 14BIT 4CHAN 5V 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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