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參數(shù)資料
型號(hào): AD7865BS-3
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: Four-Channel, Simultaneous Sampling, Fast, 14-Bit ADC
中文描述: 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP44
封裝: PLASTIC, QFP-44
文件頁數(shù): 7/19頁
文件大小: 195K
代理商: AD7865BS-3
AD7865
–7–
REV. A
Pin
Mnemonic
Description
Reference Input/Output. This pin provides access to the internal reference (+2.5 V
±
20 mV)
and also allows the internal reference to be overdriven by an external reference source (+2.5 V
±
5%). A 0.1
μ
F decoupling capacitor should be connected between this pin and AGND.
Analog Positive Supply Voltage, +5.0 V
±
5%. A 0.1
μ
F decoupling capacitor should be con-
nected between this pin and AGND.
Analog Ground. General Analog Ground. This AGND pin should be connected to the system’s
AGND plane.
Data Bit 13 is the MSB, followed by Data Bit 12 to Data Bit 6. Three-state TTL outputs.
Output coding is twos complement for AD7865-1 and AD7865-3, and straight binary for
AD7865-2.
Positive Supply Voltage for Digital section, +5.0 V
±
5%. A 0.1
μ
F decoupling capacitor
should be connected between this pin and AGND. Both DV
DD
and AV
DD
should be exter-
nally tied together.
This pin provides the positive supply voltage for the output drivers (DB0 to DB13), BUSY,
EOC
and FRSTDATA. It is normally tied to DV
DD
. V
DRIVE
should be decoupled with a
0.1
μ
F capacitor. It allows improved performance when reading during the conversion se-
quence. Also, the output data drivers may be powered by a 3 V
±
10% supply to facilitate
interfacing to 3 V processors and DSPs.
Digital Ground. Ground reference for Digital circuitry. This DGND pin should be connected
to the system’s DGND
plane. The system’s DGND and AGND planes should be connected
together at one point only, preferably at an AGND pin.
Data Bit 5 to Data Bit 4. Three-state TTL outputs.
Data Bit 3 to Data Bit 0. Bidirectional data pins. When a read operation takes place, these
pins are three-state TTL outputs. The channel select register is programmed with the data on
the DB0–DB3 pins with standard
CS
and
WR
signals. DB0 represents Channel 1 and DB3
represents Channel 4.
End-of-Conversion. Active low logic output indicating conversion status. The end of each
conversion in a conversion sequence is indicated by a low going pulse on this line.
24
V
REF
25
AV
DD
26
AGND
27–34
DB13–DB6
35
DV
DD
36
V
DRIVE
37
DGND
38, 39
40–43
DB5, DB4
DB3–DB0
44
EOC
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