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參數資料
| 型號： | AD7887ARM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | +2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOIC |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁數： | 13/16頁 |
| 文件大小： | 133K |
| 代理商： | AD7887ARM |
REV. B
AD7887
–13–
SCLK
CS
DOUT
DIN
CONTROL REGISTER DATA IS LOADED ON
THE FIRST 8 CLOCKS. PM1 = 1 AND PM0 = 1
1
16
PM1 = 1 AND PM0 = 1 TO KEEP
THE PART IN THIS MODE
1
16
THE PART POWERS UP
FROM STANDBY ON SCLK
FALLING EDGE AS PM1 = 1
AND PM0 = 1
THE PART ENTERS
STANDBY AT THE END OF
CONVERSION AS
PM1 = 1 AND PM0 = 1
4 LEADING ZEROS + CONVERSION RESULT
DATA IN
4 LEADING ZEROS + CONVERSION RESULT
DATA IN
Figure 16. Mode 4 Operation
SE RIAL INT E RFACE
Figure 17 shows the detailed timing diagrams for serial interfac-
ing to the AD7887. T he serial clock provides the conversion
clock and also controls the transfer of information to and from
the AD7887 during conversion.
CS
initiates the data transfer and conversion process. For some
modes, the falling edge of
CS
wakes up the part. In all cases, it
gates the serial clock to the AD7887 and puts the on-chip track/
hold into track mode. T he input signal is sampled on the second
rising edge of the SCLK input after the falling edge of
CS
. T hus,
the first one and one-half clock cycles after the falling edge of
CS
are when the acquisition of the input signal takes place. T his
time is denoted as the acquisition time (t
ACQ
). In modes where
the falling edge of
CS
wakes up the part, the acquisition time
must allow for the wake-up time of 5
μ
s. T he on-chip track/hold
goes from track mode to hold mode on the second rising edge of
SCLK and a conversion is also initiated on this edge. T he con-
version process takes a further fourteen and one-half SCLK
cycles to complete. T he rising edge of
CS
will put the bus back
into three-state. If
CS
is left low a new conversion will be initiated.
In dual-channel operation, the input channel that is sampled is
the one that was selected in the previous write to the Control
Register. T hus, in dual-channel operation the user must write
ahead the channel for conversion. In other words, the user must
write the channel address for the next conversion while the
present conversion is in progress.
Writing of information to the Control Register takes place on the
first eight rising edges of SCLK in a data transfer. T he Control
Register is always written to when a data transfer takes place.
However, the AD7887 can be operated in a read-only mode by
tying DIN low, thereby loading all 0s to the Control Register
every time. When operating the AD7887 in write/read mode, the
user must be careful to always set up the correct information on
the DIN line when reading data from the part.
Sixteen serial clock cycles are required to perform the conversion
process and to access data from the AD7887. In applications
where the first serial clock edge, following
CS
going low, is a
falling edge, this edge clocks out the first leading zero. T hus, the
first rising clock edge on the SCLK clock has the first leading
zero provided. In applications where the first serial clock edge,
following
CS
going low, is a rising edge, the first leading zero
may not be set up in time for the processor to read it correctly.
However, subsequent bits are clocked out on the falling edge of
SCLK so that they are provided to the processor on the follow-
ing rising edge. T hus, the second leading zero is clocked out on
the falling edge subsequent to the first rising edge. T he final bit
in the data transfer is valid on the sixteenth rising edge, having
being clocked out on the previous falling edge.
DONTC
ZERO
ZERO
REF
SIN/DUAL
CH
PM1
PM0
SCLK
1
5
6
15
DOUT
DIN
2
3
4
16
t
1
t
ACQ
t
CONVERT
t
2
t
6
t
7
t
3
t
8
DB11
DB0
DB10
DB9
THREE-
STATE
4 LEADING ZEROS
CS
THREE-
STATE
t
4
t
5
Figure 17. Serial Interface Timing Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| AD7887BR | +2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOIC |
| AD7888(中文) | 2.7 V to 5.25 V, Micro Power, 8-Channel,125kSPS,12-Bit ADC(微功耗,125kSPS,8通道12位A/D轉換器) |
| AD7888 | +2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOP |
| AD7888AR | +2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOP |
| AD7888ARU | +2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7887ARM-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 125ksps 12-bit Serial 8-Pin MSOP T/R |
| AD7887ARM-REEL7 | 功能描述:IC ADC 12BIT 2CH SRL 8-MSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:16 采樣率（每秒）:45k 數據接口:串行 轉換器數目:2 功率耗散（最大）:315mW 電壓電源:模擬和數字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數目和類型:2 個單端，單極 |
| AD7887ARMZ | 功能描述:IC ADC 12BIT 2CH SRL 8MSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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