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參數(shù)資料
型號: AD7887ARM
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: +2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOIC
中文描述: 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝: MO-187AA, MSOP-8
文件頁數(shù): 7/16頁
文件大小: 133K
代理商: AD7887ARM
REV. B
AD7887
–7–
CONT ROL RE GIST E R
T he Control Register on the AD7887 is an 8-bit, write-only register. Data is loaded from the DIN pin of the AD7887 on the rising
edge of SCLK . T he data is transferred on the DIN line at the same time as the conversion result is read from the part. T his requires
16 serial clocks for every data transfer. Only the information provided on the first eight rising clock edges (after
CS
falling edge) is
loaded to the Control Register. MSB denotes the first bit in the data stream. T he bit functions are outlined in T able I. T he contents
of the Control Register on power up is all zeros.
T able I. Control Register
MSB
DONT C
ZE RO
RE F
SIN/DUAL
CH
ZE RO
PM1
PM0
Bit
Mnemonic
Comment
7
DONT C
Don’t Care. T he value written to this bit of the Control Register is a don’t care, i.e., it doesn’t matter if
the bit is 0 or 1.
A zero must be written to this bit to ensure correct operation of the AD7887.
Reference Bit. With a 0 in this bit, the on-chip reference is enabled. With a 1 in this bit, the on-chip
reference is disabled.
Single/Dual Bit. T his bit determines whether the AD7887 operates in single-channel or dual-channel
mode. A 0 in this bit selects single-channel operation and the AIN1/V
REF
pin assumes its V
REF
function.
A 1 in this bit selects dual-channel mode and the reference voltage for the ADC is internally connected
to V
DD
and the AIN1/V
REF
pin assumes its AIN1 function as the second analog input channel. T o
obtain best performance from the AD7887, the internal reference should be disabled when operating in
the dual channel mode, i.e., REF = 1.
Channel Bit. When the part is selected for dual-channel mode, this bit determines which channel will be
converted for the next conversion. A 0 in this bit selects the AIN0 input while a 1 in this bit selects the
AIN1 input. In single-channel mode, this bit should always be 0.
A zero must be written to this bit to ensure correct operation of the AD7887.
Power Management Bits. T hese two bits decode the mode of operation of the AD7887 as described
below.
6
5
ZERO
REF
4
SIN/DUAL
3
CH
2
1, 0
ZERO
PM1, PM0
T able II. Power Management Options
PM1
PM0
Mode
0
0
Mode 1
. In this mode, the AD7887 enters shutdown if the
CS
input is 1 and is in full power mode when
CS
is 0. T hus the part comes out of shutdown on the falling edge of
CS
and enters shutdown on the
rising edge of
CS
.
Mode 2
. In this mode, the AD7887 is always fully powered up, regardless of the status of any of the logic
inputs.
Mode 3
. In this mode, the AD7887 automatically enters shutdown mode at the end of each conversion,
regardless of the state of
CS
.
Mode 4
. In this standby mode, portions of the AD7887 are powered down but the on-chip reference
voltage remains powered up. T his mode is similar to Mode 3, but allows the part to power up much
faster. T he REF bit should be 0 to ensure the on-chip reference is enabled.
0
1
1
0
1
1
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