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參數(shù)資料
| 型號： | AD7891YP-1 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | CAT5E PATCH CORD 6 FOOT BEIGE |
| 中文描述： | 8-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL/PARALLEL ACCESS, PQCC44 |
| 封裝： | PLASTIC, MO-047AC, LCC-44 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 173K |
| 代理商： | AD7891YP-1 |
AD7891
TIMING CHARACTERISTICS
1, 2
–4–
REV. A
Parameter
A, B, Y Versions
Units
μ
s max
Test Conditions/Comments
t
CONV
Parallel Interface
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
93
t
104
1.6
Conversion Time
0
35
25
5
0
35
55
35
25
5
30
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
CS
to
RD
/
WR
Setup Time
Write Pulsewidth
Data Valid to Write Setup Time
Data Valid to Write Hold Time
CS
to
RD
/
WR
Hold Time
CONVST
Pulsewidth
EOC
Pulsewidth
Read Pulsewidth
Data Access Time after Falling Edge of
RD
Bus Relinquish Time after Rising Edge of
RD
Serial Interface
t
t
11
t
13
t
t
14
t
163
t
t
17
30
20
25
25
5
15
20
0
30
0
30
20
15
10
30
ns min
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
RFS
Low to SCLK Falling Edge Setup Time
RFS
Low to Data Valid Delay
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Rising Edge to Data Valid Hold Time
SCLK Rising Edge to Data Valid Delay
RFS
to SCLK Falling Edge Hold Time
Bus Relinquish Time after Rising Edge of
RFS
t
18A4
Bus Relinquish Time after Rising Edge of SCLK
t
19
t
20
t
21
t
22
TFS
Low to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Hold Time
TFS
Low to SCLK Falling Edge Hold Time
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to
90% of +5 V) and timed from a voltage level of +1.6 V.
2
See Figures 2, 3 and 4.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
4
These times are derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
200
m
A
+1.6V
TO
OUTPUT
PIN
50pF
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
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| AD7891BP-1 | LC2MOS 8-Channel, 12-Bit High Speed Data Acquisition System |
| AD7891BP-2 | LC2MOS 8-Channel, 12-Bit High Speed Data Acquisition System |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7891YP-1REEL | 制造商:Analog Devices 功能描述:ADC Single 454.5ksps 12-bit Parallel/Serial 44-Pin PLCC T/R 制造商:Analog Devices 功能描述:ADC SGL 454.5KSPS 12-BIT PARALLEL/SERL 44PLCC - Tape and Reel |
| AD7891YPZ-1 | 功能描述:IC DAS 12BIT 8CH 44-PLCC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| AD7891YPZ-1REEL | 功能描述:IC DAS 12BIT 8CH 44-PLCC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| AD7891YS1 | 制造商:AD 功能描述:New |
| AD7891YS-1 | 制造商:Analog Devices 功能描述:ADC Single 454.5ksps 12-bit Parallel/Serial 44-Pin MQFP |
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