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參數資料
| 型號： | AD7910AKS-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70 |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封裝： | MO-203AB, SC-70, 6 PIN |
| 文件頁數： | 12/20頁 |
| 文件大?。?/td> | 1091K |
| 代理商： | AD7910AKS-REEL7 |
REV. B
–12–
AD7910/AD7920
Analog Input
Figure 8 shows an equivalent circuit of the analog input structure
of the AD7910/AD7920. The two diodes D1 and D2 provide
ESD protection for the analog input. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 300 mV. This will cause these diodes to become
forward biased and start conducting current into the substrate.
10 mA is the maximum current these diodes can conduct without
causing irreversible damage to the part. The capacitor C1 in
Figure 8 is typically about 6 pF and can be attributed primarily to
pin capacitance. The resistor R1 is a lumped component made
up of the on resistance of a switch. This resistor is typically about
100
W
. The capacitor C2 is the ADC sampling capacitor and has
a capacitance of
20 pF typically. For ac applications, removing
high frequency components from the analog input signal is
recommended by use of a band-pass filter on the relevant analog
input pin. In applications where harmonic distortion and signal-
to-noise ratio are critical, the analog input should be driven from
a low impedance source. Large source impedances will signifi-
cantly affect the ac performance of the ADC. This may necessitate
the use of an input buffer amplifier. The choice of the op amp is
a function of the particular application.
D1
D2
R1
C2
20pF
V
DD
V
IN
C1
6pF
CONVERSION PHASE – SWITCH OPEN
TRACK PHASE – SWITCH CLOSED
Figure 8. Equivalent Analog Input Circuit
Table II provides some typical performance data with various
op amps used as the input buffer for a 100 kHz input tone at room
temperature under the same setup conditions.
Table II. AD7920 Typical Performance
for Various Input Buffers, V
DD
= 3 V
Op Amp in the
Input Buffer
AD7920 SNR
Performance (dB)
AD711
AD797
AD845
72.3
72.5
71.4
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of total harmonic distortion
(THD) that can be tolerated. The THD increases as the source
impedance increases, and performance degrades (see TPC 6).
Digital Inputs
The digital inputs applied to the AD7910/AD7920 are not
limited by the maximum ratings that limit the analog input. Instead,
the digital inputs applied can go to 7 V and are not restricted
by the V
DD
+ 0.3 V limit as on the analog input. For example, if
the AD7910/AD7920 were operated with a V
DD
of 3 V, then 5 V
logic levels could be used on the digital inputs. However, it is
important to note that the data output on SDATA will still have 3 V
logic levels when V
DD
= 3 V. Another advantage of SCLK and
CS
not being restricted by the V
DD
+ 0.3 V limit is that power
supply sequencing issues are avoided. If
CS
or SCLK is applied
before V
DD
, there is no risk of latch-up as there would be on the
analog inputs if a signal greater than 0.3 V was applied prior to V
DD
.
MODES OF OPERATION
The mode of operation of the AD7910/AD7920 is selected by
controlling the logic state of the
CS
signal during a conversion.
There are two possible modes of operation, normal mode and
power-down mode. The point at which
CS
is pulled high
after the conversion has been initiated determines whether the
AD7910/AD7920 enters power-down mode. Similarly, if the
device is already in power-down mode,
CS
can control whether
it returns to normal operation or remains in power-down mode.
These modes of operation are designed to provide flexible power
management options. These options can be chosen to optimize
the power dissipation/throughput rate ratio for different applica-
tion requirements.
Normal Mode
This mode is intended for fastest throughput rate performance
because the user does not have to worry about any power-up
times; the AD7910/AD7920 remains fully powered all the time.
Figure 9 shows the general diagram of the operation of the
AD7910/AD7920 in this mode.
The conversion is initiated on the falling edge of
CS
as described
in the Serial Interface section. To ensure that the part remains
fully powered up at all times,
CS
must remain low until at least
10 SCLK falling edges have elapsed after the falling edge of
CS
.
If
CS
is brought high any time after the 10th SCLK falling edge
but before the end of the t
CONVERT
, the part will remain pow-
ered up but the conversion
will be terminated and SDATA will
go back into three-state.
For the AD7920, 16 serial clock cycles are required to complete
the conversion and access the complete conversion result. For the
AD7910, a minimum of 14 serial clock cycles is required to com-
plete the conversion and access the complete conversion result.
CS
may idle high until the next conversion or may idle low until
CS
returns high sometime prior to the next conversion, effectively
idling
CS
low.
Once a data transfer is complete (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
t
QUIET
, has elapsed by bringing
CS
low again.
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