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參數資料
| 型號： | AD7910AKS-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70 |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封裝： | MO-203AB, SC-70, 6 PIN |
| 文件頁數： | 5/20頁 |
| 文件大小： | 1091K |
| 代理商： | AD7910AKS-REEL7 |
REV. B
AD7910/AD7920
–5–
CS
SCLK
SDATA
t
2
t
6
t
3
t
4
ZERO
t
7
DB10
t
5
t
8
t
CONVERT
t
QUIET
ZERO
ZERO
DB11
DB2
DB1
DB0
B
THREE-STATE
THREE-
STATE
Z
4 LEADING ZEROS
1
2
3
4
5
13
14
15
16
t
1
Figure 2. AD7920 Serial Interface Timing Diagram
CS
SCLK
t
2
t
CONVERT
B
1
2
3
4
5
13
14
15
16
C
t
8
t
QUIET
t
ACQ
12.5(1/f
SCLK
)
1/THROUGHPUT
Figure 3. Serial Interface Timing Example
TO OUTPUT
PIN
C
L
50pF
200 A
I
OH
200 A
I
OL
1.6V
Figure 1. Load Circuit for Digital Output Timing
Specifications
TIMING EXAMPLES
Figures 2 and 3 show some of the timing parameters from the
Timing Specifications table.
Timing Example 1
From Figure 3, having f
SCLK
= 5 MHz and a throughput rate of
250 kSPS gives a cycle time of t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 4
m
s.
With t
2
= 10 ns min, this leaves t
ACQ
to be 1.49
m
s. This 1.49
m
s
satisfies the requirement of 250 ns for t
ACQ
. From Figure 3, t
ACQ
comprises 2.5(1/f
SCLK
) + t
8
+ t
QUIET
, where t
8
= 36 ns max. This
allows a value of 954 ns for t
QUIET,
satisfying the minimum re-
quirement of 50 ns.
Timing Example 2
The AD7920 can also operate with slower clock frequencies.
From Figure 3, having f
SCLK
= 3.4 MHz and a throughput rate
of 150 kSPS gives a cycle time of t
2
+ 12.5(1/f
SCLK
) + t
ACQ
=
6.66
m
s. With t
2
= 10 ns min, this leaves t
ACQ
to be 2.97
m
s. This
2.97
m
s satisfies the requirement of 250 ns for t
ACQ
. From
Figure 3, t
ACQ
comprises 2.5(1/f
SCLK
) + t
8
+ t
QUIET
, t
8
= 36 ns
max. This allows a value of 2.19
m
s for t
QUIET
, satisfying the
minimum requirement of 50 ns. As in this example and with
other slower clock values, the signal may already be acquired
before the conversion is complete, but it is still necessary to leave
50 ns minimum t
QUIET
between conversions. In this example, the
signal should be fully acquired at approximately point C in
Figure 3.
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| AD7910ARM-REEL7 | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
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