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參數(shù)資料
| 型號： | AD7923BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Four Wall Header; No. of Contacts:60; Pitch Spacing:0.1"; No. of Rows:2; Gender:Header; Body Material:Glass-filled Polyester; Contact Plating:Nickel; Leaded Process Compatible:No; Mounting Type:Through Hole RoHS Compliant: No |
| 中文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大小： | 430K |
| 代理商： | AD7923BRU |
AD7923
–11–
REV. 0
Figure 2 reflects the traditional operation of a multichannel ADC,
where each serial transfer selects the next channel for conversion.
In this mode of operation the Sequencer function is not used.
Figure 3 shows how to program the AD7923 to continuously
convert on a sequence of consecutive channels from Channel 0
to a selected final channel. To exit this mode of operation and
revert back to the traditional mode of operation of a multichannel
ADC (as outlined in Figure 2), ensure that the WRITE bit = 1
and SEQ1 = SEQ0 = 0 on the next serial transfer.
POWER-ON
DUMMY CONVERSION
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A1, A0 FOR CONVERSION.
SEQ1 = 0, SEQ0 = x
DOUT: CONVERSION RESULT FROM PREVIOUSLY
SELECTED CHANNEL A1, A0
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT A1, A0 FOR CONVERSION.
SEQ1 = 0, SEQ0 = x
WRITE BIT = 1,
SEQ1 = 0,
SEQ0 = x
CS
CS
Figure 2. SEQ1 Bit = 0, SEQ0 Bit = x Flowchart
POWER-ON
DUMMY CONVERSION
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A1, A0 FOR CONVERSION.
SEQ1 = 1, SEQ0 = 1
DOUT: CONVERSION RESULT FROM CHANNEL 0
CONTINUOUSLY CONVERTS ON A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0 UP
TO AND INCLUDING THE PREVIOUSLY SELECTED
A1, A0 IN THE CONTROL REGISTER
WRITE BIT = 0
CONTINUOUSLY CONVERTS ON THE SELECTED
SEQUENCE OF CHANNELS BUT WILL ALLOW
RANGE, CODING, ETC., TO CHANGE IN THE CON-
TROL REGISTER WITHOUT INTERRUPTING THE
SEQUENCE, PROVIDED SEQ = 1, SEQ0 = 0
WRITE BIT = 1,
SEQ1 = 1,
SEQ0 = 0
CS
CS
CS
Figure 3. SEQ1 Bit = 1, SEQ0 Bit = 1 Flowchart
CIRCUIT INFORMATION
The AD7923 is high speed, 4-channel, 12-bit, single-supply
A/D converter. The part can be operated from a 2.7 V to 5.25 V
supply. When operated from either a 5 V or 3 V supply, the
AD7923 is capable of throughput rates of 200 kSPS. The con-
version time may be as short as 800 ns when provided with a
20 MHz clock.
The AD7923 provides the user with an on-chip, track-and-hold
A/D converter, and with a serial interface housed in a 16-lead
TSSOP package. The AD7923 has four single-ended input
channels with a channel sequencer, allowing the user to select a
channel sequence through which the ADC can cycle with each
consecutive
CS
falling edge. The serial clock input accesses data
from the part, controls the transfer of data written to the ADC,
and provides the clock source for the successive approximation
A/D converter. The analog input range for the AD7923 is 0 V
to REF
IN
or 0 V to 2
￥
REF
IN
, depending on the status of Bit 1
in the Control Register. For the 0 to 2
￥
REF
IN
range, the part
must be operated from a 4.75 V to 5.25 V supply.
The AD7923 provides flexible power management options to
allow the user to achieve the best power performance for a given
throughput rate. These options are selected by programming the
Power Management bits, PM1 and PM0, in the Control Register.
CONVERTER OPERATION
The AD7923 is a 12-bit successive approximation analog-to-
digital converter based around a capacitive DAC. The AD7923
can convert analog input signals in the range 0 V to REF
IN
or 0 V
to 2
￥
REF
IN
. Figures 4 and 5 show simplified schematics of the
ADC. The ADC is comprised of Control Logic, SAR, and a
capacitive DAC, which are used to add and subtract fixed amounts
of charge from the sampling capacitor to bring the comparator
back into a balanced condition. Figure 4 shows the ADC during
its acquisition phase. SW2 is closed and SW1 is in position A. The
comparator is held in a balanced condition and the sampling
capacitor acquires the signal on the selected V
IN
channel.
V
IN
0
V
IN
3
AGND
A
B
SW1
SW2
COMPARATOR
CONTROL
LOGIC
CAPACITIVE
DAC
4k
Figure 4. ADC Acquisition Phase
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