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參數(shù)資料
| 型號(hào)： | AD7923BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Four Wall Header; No. of Contacts:60; Pitch Spacing:0.1"; No. of Rows:2; Gender:Header; Body Material:Glass-filled Polyester; Contact Plating:Nickel; Leaded Process Compatible:No; Mounting Type:Through Hole RoHS Compliant: No |
| 中文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁(yè)數(shù)： | 13/20頁(yè) |
| 文件大?。?/td> | 430K |
| 代理商： | AD7923BRU |
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AD7923
–13–
REV. 0
two address bits indicating which channel the conversion result
corresponds to, followed by the 12 bits of conversion data. For
applications where power consumption is of concern, the power-
down modes should be used between conversions or bursts of
several conversions to improve power performance. See the
Modes of Operation section.
SERIAL
INTERFACE
AD780
2.5V
AD7923
0.1 F
C/ P
0.1 F
10 F
3V
SUPPLY
5V
SUPPLY
0.1 F
10 F
AGND
AV
DD
V
IN
0
V
IN
3
0V TO REF
IN
SCLK
DOUT
CS
DIN
V
DRIVE
REF
IN
NOTE: ALL UNUSED INPUT CHANNELS MUST BE CONNECTED TO AGND
Figure 10. Typical Connection Diagram
Analog Input Selection
Any one of four analog input channels may be selected for con-
version by programming the multiplexer with the address bits
ADD1 and ADD0 in the Control Register. The channel configu-
rations are shown in Table II.
The AD7923 may also be configured to automatically cycle
through a number of channels as selected. The sequencer fea-
ture is accessed via the SEQ1 and SEQ0 bits in the Control
Register. (See Table IV). The AD7923 can be programmed to
continuously convert on a number of consecutive channels in
ascending order from Channel 0 to a selected final channel as
determined by the channel address bits ADD1 and ADD0. This
is possible if the SEQ1 and SEQ0 bits are set to 1,1. The next
serial transfer will then act on the sequence programmed by
executing a conversion on Channel 0. The next serial transfer
will result in a conversion on Channel 1, and so on, until the
channel selected via the address bits ADD1, ADD0 is reached.
It is not necessary to write to the Control Register again once a
sequencer operation has been initiated. The WRITE bit must be
set to zero or the DIN line tied low to ensure that the Control
Register is not accidently overwritten, or the sequence operation
interrupted. If the Control Register is written to at any time
during the sequence, the user must ensure that the SEQ1 and
SEQ0 bits are set to 1,0 to avoid interrupting the automatic
conversion sequence. This pattern will continue until the AD7923
is written to and the SEQ1 and SEQ0 bits are configured with
any bit combination except 1,0 resulting in the termination of
the sequence. If uninterrupted, however (WRITE bit = 0, or
WRITE bit = 1 and SEQ1 and SEQ0 bits are set to 1,0), then
upon completion of the sequence, the AD7923 sequencer will
return to the Channel 0 and commence the sequence again.
Regardless of which channel selection method is used, the 16-bit
word output from the AD7923 during each conversion will
always contain two leading zeros, two channel address bits that
the conversion result corresponds to, followed by the 12-bit
conversion result. (See the Serial Interface section.)
Digital Inputs
The digital inputs applied to the AD7923 are not limited by
the maximum ratings that limit the analog inputs. Instead, the
digital inputs applied can go to 7 V and are not restricted by the
AV
DD
+ 0.3 V limit as on the analog inputs.
Another advantage of SCLK, DIN, and
CS
not being restricted by
the AV
DD
+ 0.3 V limit is that possible power supply sequencing
issues are avoided. If
CS
, DIN, or SCLK is applied before AV
DD
,
there is no risk of latch-up as there would be on the analog inputs
if a signal greater than 0.3 V was applied prior to AV
DD
.
V
DRIVE
The AD7923 also has the V
DRIVE
feature. V
DRIVE
controls the
voltage at which the serial interface operates. V
DRIVE
allows the
ADC to easily interface to both 3 V and 5 V processors. For
example, if the AD7923 were operated with an AV
DD
of 5 V, the
V
DRIVE
pin could be powered from a 3 V supply. The AD7923
has a larger dynamic range with an AV
DD
of 5 V while still being
able to interface to 3 V processors. Care should be taken to
ensure that V
DRIVE
does not exceed AV
DD
by more than 0.3 V.
(See the Absolute Maximum Ratings section.)
R3
R2
R4
REF
IN
V
IN
0
V
IN
3
AD7923
DSP/ P
V
DD
0.1 F
V
AV
DD
V
DRIVE
DOUT
TWOS
COMPLEMENT
+REF
IN
REF
IN
–REF
IN
011…111
000…000
100…000
(= 0V)
(= 2 REF
IN
)
0V
V
R1
R1 R2 R3 R4
V
DD
V
REF
Figure 9. Handling Bipolar Signals
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