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參數資料
| 型號： | AD7947 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 3mW, 100kSPS, 14-Bit ADC in 6-Lead SOT-23 |
| 中文描述： | 3MW的，100ksps的14位ADC的6引腳SOT - 23 |
| 文件頁數： | 14/20頁 |
| 文件大小： | 480K |
| 代理商： | AD7947 |
AD7940
POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate, and then the ADC is pow-
ered down for a relatively long duration between these bursts of
several conversions. When the AD7940 is in power-down, all
analog circuitry is powered down.
Rev. 0 | Page 14 of 20
To enter power-down, the conversion process must be inter-
rupted by bringing CS high anywhere after the second falling
edge of SCLK and before the 10th falling edge of SCLK as
shown in Figure 17. Once CS has been brought high in this
window of SCLKs, the part will enter power-down, the
conversion that was initiated by the falling edge of CS will be
terminated, and SDATA will go back into three-state. If CS is
brought high before the second SCLK falling edge, the part will
remain in normal mode and will not power down. This will
avoid accidental power-down due to glitches on the CS line.
In order to exit this mode of operation and power up the
AD7940 again, a dummy conversion is performed. On the fal-
ling edge of CS, the device will begin to power up and will
continue to power up as long as CS is held low until after the
falling edge of the 10th SCLK. The device will be fully powered
up once at least 16 SCLKs (or approximately 6 μs) have elapsed
and valid data will result from the next conversion as shown in
Figure 18. If CS is brought high before the 10th falling edge of
SCLK, regardless of the SCLK frequency, the AD7940 will go
back into power-down again. This avoids accidental power-up
due to glitches on the CS line or an inadvertent burst of 8 SCLK
cycles while CS is low. So although the device may begin to
power-up on the falling edge of CS, it will power down again on
the rising edge of CS as long as it occurs before the 10th SCLK
falling edge.
0
SCLK
SDATA
1
2
10
16
THREE-STATE
CS
Figure 17. Entering Power-Down Mode
0
1
10
16
1
16
SDATA
SCLK
CS
INVALID DATA
VALID DATA
THE PART IS FULLY POWERED
UP WITH V
IN
FULLY ACQUIRED
THE PART BEGINS
TO POWER UP
t
POWER UP
Figure 18. Exiting Power-Down Mode
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