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參數資料
| 型號： | AD7947 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 3mW, 100kSPS, 14-Bit ADC in 6-Lead SOT-23 |
| 中文描述： | 3MW的，100ksps的14位ADC的6引腳SOT - 23 |
| 文件頁數： | 5/20頁 |
| 文件大小： | 480K |
| 代理商： | AD7947 |
AD7940
TIMING SPECIFICATIONS
Sample tested at initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from
a voltage level of 1.6 V.
Rev. 0 | Page 5 of 20
V
DD
= 2.50 V to 5.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
f
SCLK1
t
CONVERT
t
QUIET
Limit at T
MIN
, T
MAX
3 V
250
2.5
16 × t
SCLK
50
Unit
kHz min
MHz max
min
ns min
Description
Minimum quiet time required between bus relinquish and start of
next conversion
Minimum CS pulse width
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to SDATA high impedance
Power up time from full power-down
5 V
250
2.5
16 × t
SCLK
50
t
1
t
2
t
32
t
42
t
5
t
6
t
7
t
83
t
POWER-UP4
10
10
48
120
0.4 t
SCLK
0.4 t
SCLK
10
45
1
10
10
35
80
0.4 t
SCLK
0.4 t
SCLK
10
35
1
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
μs typ
1
Mark/space ratio for the SCLK input is 40/60 to 60/40.
2
Measured with the load circuit of
3
t
8
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
4
See the
section.
Power vs. Throughput Rate
and defined as the time required for the output to cross 0.8 V or 2.0 V.
Figure 2
Figure 2.
The measured number is then extrapolated
0
200
μ
A
I
OL
200
μ
A
I
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
Figure 2. Load Circuit for Digital Output Timing Specification
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