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參數資料
| 型號： | AD7947 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 3mW, 100kSPS, 14-Bit ADC in 6-Lead SOT-23 |
| 中文描述： | 3MW的，100ksps的14位ADC的6引腳SOT - 23 |
| 文件頁數： | 7/20頁 |
| 文件大小： | 480K |
| 代理商： | AD7947 |
AD7940
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 7 of 20
0
CS
SDATA
SCLK
6
5
4
V
DD
GND
1
2
V
IN
3
AD7940
TOP VIEW
(Not to Scale)
SOT-23
Figure 3. SOT-23 Pin Configuration
0
NC = NO CONNECT
AD7490
TOP VIEW
(Not to Scale)
MSOP
V
DD
GND
1
2
GND
3
V
IN
4
CS
SDATA
NC
SCLK
8
7
6
5
Figure 4. MSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
SOT-23
MSOP
1
1
2
2, 3
Pin No.
Mnemonic
V
DD
GND
Function
Power Supply Input. The V
DD
range for the AD7940 is from 2.5 V to 5.5 V.
Analog Ground. Ground reference point for all circuitry on the AD7940. All analog input signals should
be referred to this GND voltage.
Analog Input. Single-ended analog input channel. The input range is 0 V to V
DD
.
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from this part. This clock
input is also used as the clock source for the AD7940's conversion process.
Data Out. Logic output. The conversion result from the AD7940 is provided on this output as a serial
data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the
AD7940 consists of two leading zeros followed by 14 bits of conversion data that are provided MSB
first. This will be followed by four trailing zeroes if CS is held low for a total of 24 SCLK cycles. See the
Serial Interface section.
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7940 and framing the serial data transfer.
No Connect. This pin should be left unconnected.
3
4
4
5
V
IN
SCLK
5
7
SDATA
6
8
CS
N/A
6
NC
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