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參數(shù)資料
| 型號： | AD7992 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 2-Channel, 12-Bit ADC with I2C Compatible Interface in 10-Lead MSOP |
| 中文描述： | 2通道，12位I2C兼容接口的ADC的10引腳MSOP |
| 文件頁數(shù)： | 14/21頁 |
| 文件大小： | 266K |
| 代理商： | AD7992 |
AD7992
–14–
REV. PrH
PRELIMINARY TECHNICAL DATA
HYSTERESIS REGISTER (CH1/CH2)
The Hysteresis Register is a 16-bit read/write register, of
which only the 12 LSBs of the Register are used. The
Register stores the hysteresis value, N when using the limit
registers. Each pair of Limit registers has a dedicated hys-
teresis register. The hysteresis value determines the reset
point for the ALERT pin/Alert_Flag if a violation of the
limits has occurred. If a hysteresis value of say 8 LSBs is
required on the upper and lower limits of channel 1 then
the 12 bit word, 0000 0000 0000 1000, should be written
to Hysteresis Register CH1, the address of which is shown
in Table III. On power up, the Hysteresis Registers will
contain a value of 8 LSBs. If a different hysteresis value is
required then that value must be written to the Hysteresis
Register for the channel in question.
Table Xa. Hysteresis Register (First Read/Write)
D15
D14
D13 D12
D11
D10
D9
D8
Alert_Flag 0
0
0
B11
B10
B9
B8
Table Xb. Hysteresis Register (Second Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B0
Using the Limit Registers to Store Min/Max Conversion
Results
If fullscale, i.e. all 1s, are written to the Hysteresis regis-
ter for a channel then the DATA
HIGH
and DATA
LOW
Reg-
isters for that channel will no longer act as Limit registers
as previously described, but instead they will act as storage
registers for the maximum and minimum conversion re-
sults returned from conversions on a channel over any
given period of time. This function is useful in applica-
tions where the widest span of actual conversion results is
required rather than using the ALERT to signal an inter-
vention is necessary, e.g. monitoring temperature ex-
tremes during refrigerated goods transportation.
It must be noted that on power-up, the contents of the
DATA
HIGH
register for each channel will be fullscale,
while the contents of the DATA
LOW
registers will be
zeroscale by default so minimum and maximum conver-
sion values being stored in this way will be lost if power is
removed or cycled.
When using the limit registers to store the min and max
conversion results, the Alert_Flag bit in the limit regis-
ters, D15, is used to indicate that an alert has happened on
the other Input channel. If the Alert_Flag bit is set to 1, it
will be reset when the Conversion result returns to a value
at least N LSBs above the DATA
LOW
Register value or
below the DATA
HIGH
Register value or if bits D2 and D1
of the Configuration Register are set to 1.
The Limit Registers can be used to monitor the conver-
sion results on one or both channels. The AD7992 will
signal an Alert (in either hardware or software or both
depending on configuration) if the result moves outside
the upper or lower limit set by the user.
DATA
HIGH
REGISTER CH1/CH2
The DATA
HIGH
Register for a channel is a 16-bit read/
write register, of which only the 12 LSBs are used. The
Register stores the upper limit that will activate the
ALERT output and/or the Alert_Flag bit in the Conver-
sion Result Register. If the value in the Conversion Result
Register is greater than the value in the DATA
HIGH
Regis-
ter, then the Alert_Flag bit is set to 1 and the ALERT pin
is activated (the latter is true if ALERT is enabled in the
Configuration Register). When the conversion result re-
turns to a value at least N LSBs below the DATA
HIGH
Register value the ALERT output pin and Alert_Flag bit
will be reset. The value of N is taken from the 12-bit
Hysteresis register associated with that channel. The
ALERT pin can also be reset by writing to bits D2,D1 in
the Configuration Register.
Table VIIIa. DATA
HIGH
Register (First Read/Write)
D15
D14
D13 D12
D11
D10
D9
D8
Alert_Flag 0
0
0
B11
B10
B9
B8
Table VIIIb. DATA
HIGH
Register (Second Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B0
DATA
LOW
REGISTER CH0/CH1
The DATA
LOW
Register for a channel is a 16-bit read/
write register, of which only the 12 LSBs are used. The
Register stores the lower limit that will activate the
ALERT output and/or the Alert_Flag bit in the conver-
sion result register. If the value in the Conversion Result
Register is less than the value in the DATA
LOW
Register,
then the Alert_Flag bit is set to 1 and the ALERT pin is
activated (the latter is true if ALERT is enabled in the
Configuration Register). When the Conversion result re-
turns to a value at least N LSBs above the DATA
LOW
Register value the ALERT ouput pin and Alert_Flag bit
will be reset. The value of N is taken from the 12-bit
Hysteresis register associated with that channel. The
ALERT pin can also be reset by writing to bit D2,D1 in
the Configuration Register.
Table IXa. DATA
LOW
Register (First Read/Write)
D15
D14
D13 D12
D11
D10
D9
D8
Alert_Flag 0
0
0
B11
B10
B9
B8
Table IXb. DATA
LOW
Register (Second Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B0
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