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參數資料
| 型號： | AD7992BRM-1 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2-Channel, 12-Bit ADC with I2C Compatible Interface in 10-Lead MSOP |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | MO-187-BA, MSOP-10 |
| 文件頁數： | 13/21頁 |
| 文件大小： | 266K |
| 代理商： | AD7992BRM-1 |
AD7992
–13–
REV. PrH
PRELIMINARY TECHNICAL DATA
Bit
D7
D6
Mnemonic
DONTCARE
Single/Dual
Comment
The value written to this bit determines the functionality of the V
IN
2/REF
IN
pin. When this bit
is 1 the pin takes on its Reference Input Function, REF
IN
, making the AD7992 a single
channel part. When this bit is a 0 the pin becomes a second analog input pin, V
IN
2, making the
AD7992 a Dual channel part..
These two channel address bits select which analog input channel is to be converted. A 1 in any
of bits D5 or D4 selects a channel for conversion. If more than one channel bit is set this
indicates that the alternating channel sequence is to be used. Table V shows how these two
channel address bits are decoded. If D5 is selected the part will operate in Dual channel mode,
with the Reference for the ADC being taken from the Supply voltage( D6 set to 0 for Dual
channel mode).
The value written to this bit of the Control Register determines whether the filtering on SDA
and SCL is enabled or to be bypassed. If this bit is a 1 then the the filtering is enabled, if it is
a 0, then the filtering is bypassed.
The hardware ALERT function is enabled if this bit is set to 1 and disabled if set to 0. This bit
is used in conjunction with the BUSY/ALERT bit to determine if the ALERT/BUSY pin will
act as an ALERT or a BUSY function. (See Table VI.)
This bit is used in conjunction with the ALERT EN bit to determine if the ALERT/BUSY
output, pin 8, will act as an ALERT or BUSY function (see TABLE V1), or if pin 8 is
configured as an ALERT output pin, if it is to be reset. When reading the Configuration
registerD1 will always be a 0 when D2 is a 1.
This bit determines the active polarity of the ALERT/BUSY pin regardless of whether it is
configured as an ALERT or BUSY output. It is active low if this bit is set to 0, and it is active
high if set to 1.
D5, D4 CH2,CH1
D3
FLTR
D2
ALERT EN
D1
BUSY/ALERT
D0
BUSY/ALERT
POLARITY
Table VI. ALERT/BUSY Function
D2
D1
ALERT/BUSY Pin Configuration
0
0
Pin does not provide any interrupt signal.
0
1
Pin configured as a BUSY output.
1
0
Pin configured as an ALERT output.
1
1
Resets ALERT output pin, Alert_Flag bit in
Conversion Result Reg, and entire Alert
Status Reg ( if any active).
CONVERSION RESULT REGISTER
The Conversion Result Register is a 16-bit read-only reg-
ister which stores the conversion reading from the ADC in
Straight Binary format. A two Byte read operation is nec-
essary to read data from this register. Table VIIa shows
the contents of the first byte to be read while Table VIIb
show the contents of the second byte to be read from
AD7992.
Table VIIa. Conversion Value Register (First Read)
D15
D14
D13
D12
D11
D10
D9
D8
Alert_Flag Zero
Zero CH I.D. MSB B10
B9
B8
Table VIIb. Conversion Value Register (Second Read)
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B0
The AD7992 conversion result consists of an Alert_Flag
bit, two leading zeros, a Channel Identifier bit and the 12
bit data result.
The Alert_Flag bit indicates whether the conversion result
being read has violated a limit register associated with the
channel. This is followed by two leading zeros and a
Channel Indentifier bit indicating which channel the con-
version result corresponds to. The 12-bit conversion result
then follows MSB first.
Table V. Channel Selection
D5
CH2 CH1
D4
Analog Input Channel
0
0
No Conversion
0
1
Convert on V
IN
1
Convert on V
IN
2
Sequence between Channel 1 and Channel 2,
beginning with Ch1
1
0
1
1
LIMIT REGISTERS
The AD7992 has two pairs of limit registers, each to store
high and low conversion limits for both analog input
channels. Each pair of limit registers has an associated
hysteresis register. All six registers are 16-bits wide, of
which only the 12 LSBs of each are used. On power-up,
the contents of the DATA
HIGH
register for each channel
will be fullscale, while the contents of the DATA
LOW
reg-
isters will be zeroscale by default.
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