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參數(shù)資料
| 型號： | AD7992BRM-1 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2-Channel, 12-Bit ADC with I2C Compatible Interface in 10-Lead MSOP |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | MO-187-BA, MSOP-10 |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 266K |
| 代理商： | AD7992BRM-1 |
AD7992
–15–
REV. PrH
PRELIMINARY TECHNICAL DATA
CYCLE TIMER REGISTER
The Cycle Timer Register is a 8-bit read/write register,
which stores the conversion interval value for the Auto-
matic Cycle mode of the AD7992, see Modes of Opera-
tion section. Bits D3 - D5 of the Cycle Timer Register are
unused and should contain 0’s at all times. On power up,
the Cycle Timer Register will contain all 0s, thus dis-
abling the Automatic Cycle operation of the AD7992. To
enable the Automatic Cycle Mode the user must write to
the Cycle Timer Register, selecting the required conver-
sion interval. Table XIIa shows the structure of the Cycle
Timer register while Table XIIb shows how the bits in
this register are decoded to provide various automatic
sampling intervals.
Table XIIa. Cycle Timer Register
D7
D6
D5
D4
D3
D2
D1
D0
Sample Bit Trial 0
Dealy
Delay
0
0
Cyc* Cyc*Cyc*
Bit2
Bit1 Bit0
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at Power-up
Table XIIb. Cycle Timer Intervals
CYC Reg Value(D2,D1,D0)
Conversion Interval
000
001
010
011
100
101
110
111
Mode not selected
T
CONVERT
x 32
T
CONVERT
x 64
T
CONVERT
x 128
T
CONVERT
x 256
T
CONVERT
x 512
T
CONVERT
x 1024
T
CONVERT
x 2048
ALERT STATUS REGISTER
The Alert Status Register is a 8-bit read/write register, of
which only the four LSBs are used. This register provides
information on an Alert event. If a conversion results in
activating the ALERT pin or the Alert_Flag bit in the
Conversion Result Register, as described in the Limit
Registers section, then the Alert Status Register may be
read to gain further information. It contains 2 status bits
per channel, one corresponding to the DATA
HIGH
limit
and the other to the DATA
LOW
limit. Whichever bit has a
status of 1 will show where the violation occured, i.e. on
which channel and whether on upper or lower limit. If a
second alert event occurs on the other channel between
receiving the first alert and interrogating the Alert Status
register then the corresponding bit for that Alert event will
be set also.
The entire contents of the Alert Status register may be
cleared by writing 1,1, to bits D2 and D1 in the Configu-
ration register as shown in Table VI. This may also be
acheived by ‘writing’ all 1’s to the Alert Status Register
itself. This means that if the Alert Status Register is ad-
dressed for a write which is all 1’s, then the contents of the
Alert Status Register will then be cleared or resest to all
0’s. Alternatively, an individual active Alert bit(s) may be
reset within the Alert Status Register by performing a
write of ‘1’ to that bit alone. The advantage of this is that
once an Alert event has been serviced, that particular bit
can be reset, e.g. CH1
LO
, without clearing the entire con-
tents of the Alert Status Register, thus preserving the status
of any additional Alert, e.g. CH2
HI
, which has occured
while servicing the first. If it is not necessary to clear an
Alert directly after servicing then obviously the Alert Sta-
tus register may be read again immediately to look for any
new Alerts, bearing in mind that the one just serviced will
still be active.
Table XIa. Alert Status Register
D6
D5
D4
D7
D3
D2
D1
D0
0
0
0
0
CH2
HI
CH2
LO
CH1
HI
CH1
LO
Table XIb. Alert Status Register Bit Function
Description
Bit Mnemonic Comment
D0 CH1
LO
Violation of DATA
LOW
limit on Channel
1 if this bit set to 1, no violation if 0.
D1 CH1
HI
Violation of DATA
HIGH
limit on Chan
nel 1 if this bit set to 1, no violation if 0.
D2 CH2
LO
Violation of DATA
LOW
limit on Channel
2 if this bit set to 1, no violation if 0.
D3 CH2
HI
Violation of DATA
HIGH
limit on Chan
nel 2 if this bit set to 1, no violation if 0.
T
CONVERT
is equivalent to the conversion time of the ADC.
It is recommended that no I
2
C Bus activity occurs when a
conversion is taking place. However if this is not possible,
e.g. when operating in Mode 2 or the Automatic Cycle
mode, therefore in order to maintain the performance of
the ADC, Bits D7 and D6 in the cycle timer register are
used to delay critical sample intervals and bit trials from
occurring while there is activity on the I
2
C Bus. This may
have the effect of increasing the Conversion time. When
bits D7 and D6 are both 0, the bit trial and sample inter-
val delaying mechanism will be implemented. The default
setting of D7 and D6 is 0. However if bit trial delays
extend longer than 1 μs the conversion will terminate.
When D7 is 0 the Sampling instant delay will be imple-
mented. When D6 is 0 the bit trial delay will be imple-
mented. To turn off both set D7 and D6 to 1.
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