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參數資料
型號: AD8009
廠商: Analog Devices, Inc.
英文描述: 1 GHz, 5,500 V/us Low Distortion Amplifier
中文描述: 1千兆赫,5,500 V的/我們的低失真放大器
文件頁數: 11/12頁
文件大小: 229K
代理商: AD8009
AD8009
–11–
REV. B
Driving a Capacitive Load
A capacitive load, like that presented by some A/D converters,
can sometimes be a challenge for an op amp to drive depending
on the architecture of the op amp. Most of the problem is
caused by the pole created by the output impedance of the op
amp and the capacitor that is driven. This creates extra phase
shift that can eventually cause the op amp to become unstable.
One way to prevent instability and improve settling time when
driving a capacitor is to insert a resistor in series between the op
amp output and the capacitor. The feedback resistor is still
connected directly to the output of the op amp, while the series
resistor provides some isolation of the capacitive load from the
op amp output.
10 F
+
0.1 F
0.001 F
10 F
+
0.1 F
0.001 F
AD8009
49.9
+5V
5V
3
2
4
R
T
R
S
C
L
50pF
2V
STEP
7
6
R
F
R
G
G = + 2: R
F
= 301 = R
G
G = + 10: R
F
= 200 , R
G
= 22.1
Figure 39. Capacitive Load Drive Circuit
Figure 39 shows such a circuit with an AD8009 driving a 50 pF
load. With R
S
= 0, the AD8009 circuit will be unstable. For a
gain of +2 and +10, it was found experimentally that setting R
S
to 42.2
will minimize the 0.1% settling time with a 2 V step at
the output. The 0.1% settling time was measured to be 40 ns with
this circuit.
For smaller capacitive loads, a smaller R
S
will yield optimal
settling time, while a larger R
S
will be required for larger
capacitive loads. Of course, a larger capacitance will always
require more time for settling to a given accuracy than a smaller
one, and this will be lengthened by the increase in R
S
required.
At best, a given RC combination will require about 7 time
constants by itself to settle to 0.1%, so a limit will be reached
where too large a capacitance cannot be driven by a given
op amp and still meet the system’s required settling time
specification.
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相關代理商/技術參數
參數描述
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