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參數(shù)資料
| 型號： | AD802-155KR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Clock Recovery and Data Retiming Phase-Locked Loop |
| 中文描述： | PHASE LOCKED LOOP, PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 253K |
| 代理商： | AD802-155KR |
REV. B
–2–
AD800/AD802–SPECIFICATIONS
(V
EE
= V
MN
to V
MAX
, V
CC
= GND T
A
= T
MN
to T
MAX
, Loop Damping
Factor = 5, unless otherwse noted)
AD800-45BQ
Min
T yp
AD800-52BR
T yp
AD802-155KR/BR
Min
T yp
Parameter
1
Condition
Max
Min
Max
Max
Units
NOMINAL CENT ER FREQUENCY
44.736
51.84
155.52
MHz
°
C
°
C
OPERAT ING T EMPERAT URE
RANGE (T
MIN
to T
MAX
)
T RACK ING RANGE
K Grade
B Grade
0
–40
70
85
–40
85
–40
85
43
45.5
49
53
155
156
Mbps
CAPT URE RANGE
43
45.5
49
53
155
156
Mbps
ST AT IC PHASE ERROR
ρ
= 1, T
= +25
°
C,
V
EE
= –5.2 V
ρ
= 1
2
3
10
11.5
2
3
10
11.5
14
18
30
37
Degrees
Degrees
RECOVERED CLOCK SK EW
t
RCS
(Figure 1)
t
SU
(Figure 1)
0.2
0.6
1
0.2
0.6
1
0.2
0.8
1
ns
SET UP T IME
2.06
2.37
ns
T RANSIT IONLESS DAT A RUN
240
240
240
Bit Periods
OUT PUT JIT T ER
ρ
= 1
2
7
–1 PRN Sequence
2
23
–1 PRN Sequence
2
2.5
2.5
2
2.5
2.5
3.5
5.4
5.4
Degrees rms
Degrees rms
Degrees rms
4.7
4.7
4.7
4.7
9.7
9.7
JIT T ER T OLERANCE
f = 10 Hz
f = 2.3 kHz
f = 30 kHz
f = 1 MHz
f = 30 Hz
f = 300 Hz
f = 2 kHz
f = 20 kHz
f = 6.5 kHz
f = 65 kHz
2,500
2,500
3,000
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
6.5
0.47
0.47
830
83
7.4
0.47
2.0
0.26
7.6
0.9
JIT T ER T RANSFER
Damping Factor
Capacitor, C
ζ
= 1, Nominal
ζ
= 5, Nominal
ζ
= 10, Nominal
Peaking
ζ
= 1, Nominal
ζ
= 5, Nominal
ζ
= 10, Nominal
Bandwidth
8.2
0.22
0.82
6.8
0.15
0.68
2.2
0.047
0.22
nF
μ
F
μ
F
T
A
= +25
°
C, V
EE
= –5.2 V
T
A
= +25
°
C, V
EE
= –5.2 V
T
A
= +25
°
C, V
EE
= –5.2 V
2
0.08
0.02
45
2
0.08
0.02
52
2
0.08
0.02
130
dB
dB
dB
kHz
ACQUISIT ION T IME
ρ
= 1/2
T
A
= +25
°
C
V
EE
= –5.2 V
POWER SUPPLY
Voltage (V
MIN
to V
MAX
)
Current
ζ
= 1
ζ
= 5
ζ
= 10
1
×
10
4
3
×
10
5
8
×
10
5
8
×
10
5
1
×
10
4
3
×
10
5
8
×
10
5
8
×
10
5
1.5
×
10
4
4
×
10
5
8
×
10
5
Bit Periods
1.4
×
10
6
Bit Periods
Bit Periods
T
A
= +25
°
C
T
A
= +25
°
C, V
EE
= –5.2 V
–4.5
–5.2
125
–5.5
170
180
–4.5
–5.2
125
–5.5
170
180
–4.5
–5.2
140
–5.5
180
205
Volts
mA
mA
INPUT VOLT AGE LEVELS
Input Logic High, V
IH
Input Logic Low, V
IH
OUT PUT VOLT AGE LEVELS
Output Logic High, V
OH
Output Logic Low, V
OL
INPUT CURRENT LEVELS
Input Logic High, I
IH
Input Logic Low, I
IL
OUT PUT SLEW T IMES
Rise T ime (t
R
)
Fall T ime (t
F
)
SYMMET RY
Recovered Clock Output
T
A
= +25
°
C
–1.084
–1.95
–0.72
–1.594
–1.084
–1.95
–0.72
–1.594
–1.084
–1.95
–0.72
–1.594
Volts
Volts
T
A
= +25
°
C
–1.084
–1.95
–0.72
–1.60
–1.084
–1.95
–0.72
–1.60
–1.084
–1.95
–0.72
–1.60
Volts
Volts
T
A
= +25
°
C
125
80
125
80
125
80
μ
A
μ
A
T
= +25
°
C
20%–80%
80%–20%
ρ
= 1/2, T
= +25
°
C
V
EE
= –5.2 V
0.75
0.75
1.5
1.5
0.75
0.75
1.5
1.5
0.75
0.75
1.5
1.5
ns
ns
45
55
45
55
45
55
%
NOT ES
1
Refer to Glossary for parameter definition.
Specifications subject to change without notice.
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