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參數資料
| 型號： | AD8030 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, High Speed Rail-to-Rail Input/Output Amplifier |
| 中文描述： | 低功耗，高速軌到軌輸入/輸出放大器 |
| 文件頁數： | 6/20頁 |
| 文件大小： | 649K |
| 代理商： | AD8030 |
AD8029/AD8030/AD8040
ABSOLUTE MAXIMUM RATINGS
Table 4. AD8029/AD8030/AD8040 Stress Ratings
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
Rev. A | Page 6 of 20
Rating
12.6 V
See Figure 6
±V
S
± 0.5 V
±1.8 V
–65°C to +125°C
–40°C to +125°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8029/AD8030/
AD8040 package is limited by the associated rise in junction
temperature (T
J
) on the die. The plastic encapsulating the die
locally reaches the junction temperature. At approximately
150°C, which is the glass transition temperature, the plastic
changes its properties. Even temporarily exceeding this
temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric
performance of the AD8029/AD8030/AD8040. Exceeding a
junction temperature of 175°C for an extended period can
result in changes in silicon devices, potentially causing failure.
The still-air thermal properties of the package and PCB (θ
JA
),
ambient temperature (
T
A
), and the total power dissipated in the
package (
P
D
) determine the junction temperature of the die. The
junction temperature can be calculated as
T
J
=
T
A
+ (
P
D
×
θ
JA
)
The power dissipated in the package (
P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (
V
S
) times the
quiescent current (
I
S
). Assuming the load (
R
L
) is referenced to
midsupply, the total drive power is
V
S
/2 × I
OUT
, some of which is
dissipated in the package and some in the load (V
OUT
× I
OUT
).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
P
D
=
Quiescent Power
+ (
Total Drive Power
–
Load Power
)
(
)
L
OUT
R
L
OUT
R
S
S
S
D
V
V
V
I
V
P
2
–
2
×
+
×
=
RMS output voltages should be considered. If
R
L
is referenced to
V
S
–, as in single-supply operation, then the total drive power is
V
S
× I
OUT
.
If the rms signal levels are indeterminate, consider the worst
case, when
V
OUT
=
V
S
/4 for
R
L
to midsupply:
(
)
(
)
L
S
R
S
S
D
V
I
V
P
2
4
+
×
=
In single-supply operation with
R
L
referenced to
V
S
–, worst case
is
V
OUT
=
V
S
/2.
Airflow will increase heat dissipation, effectively reducing θ
JA
.
Also, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes will
reduce the θ
JA
. Care must be taken to minimize parasitic capaci-
tances at the input leads of high speed op amps, as discussed in
the PCB Layout section.
Figure 6 shows the maximum safe power dissipation in the
package versus the ambient temperature for the SOIC-8
(125°C/W), SOT23-8 (160°C/W), SOIC-14 (90°C/W),
TSSOP-14 (120°C/W), and SC70-6 (208°C/W) packages on a
JEDEC standard 4-layer board. θ
JA
values are approximations.
–40
–20–10
–30
0
10 20 30 40 50 60 70 80 90 100110120
AMBIENT TEMPERATURE (°C)
2.5
M
1.0
0.5
1.5
2.0
0
SOIC-8
TSSOP-14
SOIC-14
SOT-23-8
SC70-6
0
Figure 6. Maximum Power Dissipation
Output Short Circuit
Shorting the output to ground or drawing excessive current
from the AD8029/AD8030/AD8040 could cause catastrophic
failure.
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