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參數(shù)資料
| 型號(hào)： | AD8037-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | MB 26C 26#20 PIN PLUG |
| 中文描述： | 低失真，寬帶電壓反饋鉗放大器 |
| 文件頁數(shù)： | 21/23頁 |
| 文件大小： | 387K |
| 代理商： | AD8037-EB |
AD8036/AD8037
REV. A
–21–
Layout Considerations
The specified high speed performance of the AD8036 and
AD8037 requires careful attention to board layout and compo-
nent selection. Proper RF design techniques and low pass para-
sitic component selection are mandatory.
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance path. The ground plane should be removed from the
area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply and input clamp by-
passing (see Figure 83). One end should be connected to the
ground plane and the other within 1/8 inch of each power and
clamp pin. An additional large (0.47
μ
F–10
μ
F) tantalum elec-
trolytic capacitor should be connected in parallel, though not
necessarily so close, to supply current for fast, large signal
changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the in-
verting input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50
or 75
and be properly termi-
nated at each end.
Evaluation Board
An evaluation board for both the AD8036 and AD8037 is avail-
able that has been carefully laid out and tested to demonstrate
that the specified high speed performance of the device can be
realized. For ordering information, please refer to the Ordering
Guide.
The layout of the evaluation board can be used as shown or
serve as a guide for a board layout.
IN
R
O
1k
V
V
OUT
0.1
m
F
AD8036/
AD8037
V
H
0.1
m
F
V
L
R
S
–V
S
+V
S
–V
S
+V
S
R
G
R
F
1k
V
–V
S
+V
S
R
T
NONINVERTING CONFIGURATION
C5
10
m
F
+V
S
–V
S
C3
0.1
m
F
C1
0.01
m
F
C6
10
m
F
C4
0.1
m
F
C2
0.01
m
F
OPTIONAL
SUPPLY BYPASSING
Figure 83. Noninverting Configurations for Evaluation
Boards
Table I.
AD8036A
Gain
+10
AD8037A
Gain
+10
Component
+1
+2
+100
+2
+100
R
F
R
G
R
O
(Nominal)
R
S
R
T
(Nominal)
Small Signal BW (MHz)
140
274
274
49.9
100
49.9
90
2 k
221
49.9
100
49.9
10
2 k
20.5
49.9
100
49.9
1.3
274
274
49.9
100
49.9
275
2 k
221
49.9
100
49.9
21
2 k
20.5
49.9
100
49.9
3
49.9
130
49.9
240
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