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參數(shù)資料
| 型號： | AD8123ACPZ-R7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Triple Differential Receiver with Adjustable Line Equalization |
| 中文描述： | LINE RECEIVER, QCC40 |
| 封裝： | 6 X 6MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 618K |
| 代理商： | AD8123ACPZ-R7 |
AD8123
APPLICATIONS INFORMATION
BASIC OPERATION
The AD8123 is easy to apply seeing that it contains everything
on-chip that is needed for cable loss compensation. Figure 20
shows a basic application circuit (power supplies not shown)
with common-mode sync pulse extraction that is compatible
with the common-mode sync pulse encoding technique used in
the
AD8134
,
AD8147
, and
AD8148
triple differential drivers. If
sync extraction is not required, the terminations can be single
100 Ω resistors, and the comparator inputs can be left floating.
In Figure 20, the AD8123 is feeding a high impedance input,
such as a delay line or crosspoint switch, and the additional gain
of two that makes up for double termination loss is not required.
COMPARATORS
In addition to general-purpose applications, the two on-chip
comparators can be used to extract video sync pulses from the
received common-mode voltages or to receive differential digital
information. Built-in hysteresis helps to eliminate false triggers
from noise. The Sync Pulse Extraction Using Comparators
section describes the sync extraction details.
Rev. 0 | Page 11 of 16
The comparator outputs have nearly 0 Ω output impedance and
are designed to drive source-terminated transmission lines. The
source termination technique uses a resistor in series with each
comparator output such that the sum of the comparator source
resistance (≈0 Ω) and the series resistor equals the transmission
line characteristic impedance. The load end of the transmission
line is high impedance. When the signal is launched into the source
termination, its initial value is one-half of its source value because
its amplitude is divided by two in the voltage divider formed by
the source termination and the transmission line. At the load,
the signal experiences nearly 100% positive reflection due to the
high impedance load and is restored to nearly its full value. This
technique is commonly used in PCB layouts that involve high
speed digital logic.
Figure 19 shows how to apply the comparators with source
termination when driving a 50 Ω transmission line that is high
impedance at its receive end.
0
49.9
HIGH-Z
Z
0
= 50
Figure 19. Using Comparator with Source Termination
18
RED
BLUE
GREEN
CMV
RED CMV
BLUE CMV
AD8123
15
12
6
4
V
PEAK
V
POLE
V
GAIN
26
27
25
23
28
V
OFFSET
0
HSYNC OUT
VSYNC OUT
32
31
GREEN
35
34
38
37
3
2
7
8
RECEIVED
RED VIDEO
RECEIVED
GREEN VIDEO
RECEIVED
BLUE VIDEO
RED VIDEO OUT
GREEN VIDEO OUT
BLUE VIDEO OUT
ANALOG
CONTROL
INPUTS
POWER DOWN
CONTROL
GND REFERENCE
24, 39
PD
1
2
1k
1k
49.9
49.9
49.9
475
49.9
49.9
49.9
47pF
47pF
Figure 20. Basic Application Circuit with Common-Mode Sync Extraction
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD8123ACPZ-R71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Triple Differential Receiver with Adjustable Line Equalization |
| AD8123ACPZ-RL | 功能描述:IC RCVR TRPL DIFF EQUAL 40LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD8123ACPZ-RL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Triple Differential Receiver with Adjustable Line Equalization |
| AD8123ACPZ-TR | 制造商:Analog Devices 功能描述:TRIPLE EQUALIZER - Tape and Reel |
| AD8124 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Triple Differential Receiver with 200 Meter Adjustable Cable Equalization |
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