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參數(shù)資料
| 型號： | AD8123ACPZ-R7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Triple Differential Receiver with Adjustable Line Equalization |
| 中文描述： | LINE RECEIVER, QCC40 |
| 封裝： | 6 X 6MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 618K |
| 代理商： | AD8123ACPZ-R7 |
AD8123
ABSOLUTE MAXIMUM RATINGS
Rev. 0 | Page 5 of 16
Table 2.
Parameter
Supply Voltage
Power Dissipation
Input Voltage (any input)
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
Rating
11 V
See Figure 3
V
S
0.3V to V
S+
+ 0.3V
65°C to +125°C
40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, θ
JA
is
specified for the device soldered in a circuit board in still air.
Table 3. Thermal Resistance with the Underside Pad
Connected to the Plane
Package Type/PCB Type
40-Lead LFCSP/4-Layer
θ
JA
29
Unit
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8123 package
is limited by the associated rise in junction temperature (T
J
) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8123. Exceeding a junction temperature
of 175°C for an extended time can result in changes in the
silicon devices, potentially causing failure.
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). The power dissipation due to each load
current is calculated by multiplying the load current by the
voltage difference between the associated power supply and the
output voltage. The total power dissipation due to load currents
is then obtained by taking the sum of the individual power
dissipations. RMS output voltages must be used when dealing
with ac signals.
Airflow reduces θ
JA
. In addition, more metal directly in contact
with the package leads from metal traces, through holes, ground,
and power planes reduces the θ
JA
. The exposed paddle on the
underside of the package must be soldered to a pad on the PCB
surface that is thermally connected to a solid plane (usually the
ground plane) to achieve the specified θ
JA
.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 40-lead LFCSP
(29°C/W) on a JEDEC standard 4-layer board with the underside
paddle soldered to a pad that is thermally connected to a PCB
plane. θ
JA
values are approximations.
0
0
–40
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
M
1
2
3
4
5
6
7
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
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| AD8123ACPZ-TR | 制造商:Analog Devices 功能描述:TRIPLE EQUALIZER - Tape and Reel |
| AD8124 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Triple Differential Receiver with 200 Meter Adjustable Cable Equalization |
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