- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373937 > AD8123ACPZ-RL (ANALOG DEVICES INC) Triple Differential Receiver with Adjustable Line Equalization PDF資料下載
參數(shù)資料
| 型號： | AD8123ACPZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Triple Differential Receiver with Adjustable Line Equalization |
| 中文描述： | LINE RECEIVER, QCC40 |
| 封裝： | 6 X 6MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 618K |
| 代理商： | AD8123ACPZ-RL |
AD8123
THEORY OF OPERATION
The AD8123 is a unity-gain, triple, wideband, low noise analog
line equalizer that compensates for losses in UTP and coaxial
cables up to 300 meters in length. The 3-channel architecture is
targeted at high resolution RGB applications but can be used in
HD YPbPr applications as well.
Three continuously adjustable control voltages, common
to the RGB channels, are available to the designer to provide
compensation for various cable lengths as well as for variations
in the cable itself. The V
PEAK
input is used to control the amount
of high frequency peaking. V
PEAK
is the primary control that is
used to compensate for frequency and cable-length dependent,
high frequency losses that are present due to the skin effect of
the cable. A second control pin, V
GAIN
, is used to adjust broadband
gain to compensate for low frequency flat losses present in the
cable. A third control, V
POLE
, is used to move the positions of the
equalizer poles and can be linearly derived from V
PEAK
, as illustrated
in the Typical Performance Characteristics and Applications
Information sections, for UTP and coaxial cables. Finally, an
output offset adjust control, V
OFFSET
, allows the designer to shift
the output dc level.
The AD8123 has a high impedance differential input that makes
termination simple and allows dc-coupled signals to be received
directly from the cable. The AD8123 input can also be used in a
single-ended fashion in coaxial cable applications. For differential
systems that require very high CMRR, a triple differential
receiver, such as the
AD8143
or
AD8145
, can be placed in
front of the AD8123.
The AD8123 has a low impedance output that is capable of
driving a 150 Ω load. For systems where the AD8123 has to
drive a high impedance capacitive load, it is recommended that
a small series resistor be placed between the output and load to
buffer the capacitance. The resistor should not be so large as to
reduce the overall bandwidth to an unacceptable level.
Rev. 0 | Page 10 of 16
The AD8123 is designed such that systems that use short-to-
medium-length cables do not pay a noise penalty for excess gain
that they do not require. The high gain is only available for
longer length systems where it is required. This feature is built
into the V
PEAK
control and is transparent to the user.
Two comparators are provided on-chip that can be used for
sync pulse extraction in systems that use sync-on-common
mode encoding. Each comparator has very low output impedance
and can therefore be used in a source-only cable termination
scheme by placing a series resistor equal to the cable characteristic
impedance directly on the comparator output. Additional
details are provided in the Applications Information section.
INPUT COMMON-MODE VOLTAGE RANGE
CONSIDERATIONS
When using the AD8123 as a receiver, it is important to ensure
that its input common-mode voltage stays within the specified
range. The received common-mode level is calculated by adding
the common-mode level of the driver, the single-ended peak
amplitude of the received signal, the amplitude of any sync
pulses, and the other induced common-mode signals, such as
ground shifts between the driver and the AD8123 and pickup
from external sources, such as power lines and fluorescent
lights. See the Applications Information section for more details.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD8129AR | Low-Cost 270 MHz Differential Receiver Amplifiers |
| AD8129ARM | Low-Cost 270 MHz Differential Receiver Amplifiers |
| AD8129ARM-REEL3 | Low-Cost 270 MHz Differential Receiver Amplifiers |
| AD8129ARM-REEL72 | Low-Cost 270 MHz Differential Receiver Amplifiers |
| AD8130 | Low-Cost 270 MHz Differential Receiver Amplifiers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8123ACPZ-RL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Triple Differential Receiver with Adjustable Line Equalization |
| AD8123ACPZ-TR | 制造商:Analog Devices 功能描述:TRIPLE EQUALIZER - Tape and Reel |
| AD8124 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Triple Differential Receiver with 200 Meter Adjustable Cable Equalization |
| AD8124ACPZ | 功能描述:IC HS RCVR EQUALIZER 40VFQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD8124ACPZ-R7 | 功能描述:IC RCVR TRPL DIFF EQUAL 40LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。