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參數資料
| 型號： | AD8150-EVAL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 33 x 17, 1.5 Gbps Digital Crosspoint Switch |
| 中文描述： | 33 × 17，1.5 Gbps的數字交叉點開關 |
| 文件頁數： | 20/35頁 |
| 文件大小： | 995K |
| 代理商： | AD8150-EVAL |
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AD8150
–20–
REV. 0
The power dissipated in the data path outputs is affected by several
factors. The
fi
rst is whether the outputs are enabled or disabled.
The worst case occurs when all of the outputs are enabled.
The current consumed by the data path logic can be approxi-
mated by:
I
CC
= 30
mA
+ [4.5
mA
+ (
I
OUT
/20
mA
×
3
mA
)]
×
(#
of outputs enabled
)
This says that there will always be a minimum of 30 mA flow-
ing. I
CC
will increase by a factor that is proportional to both the
number of enabled outputs and the programmed output current.
The power dissipated in this circuit section will simply be the
voltage of this section (V
CC
–
V
EE
) times the current. For a worst
case, assume that V
CC
–
V
EE
is 5.0 V, all outputs are enabled
and the programmed output current is 25 mA. The power dissi-
pated by the data path logic will be:
P
= 5.0
V
{25
mA
+ [4.5
mA
+ (25
mA
/20
mA
×
3
mA
)]
×
17} = 826
mW
The power dissipated by the output current depends on several
factors. These are the programmed output current, the voltage
drop from a logic low output to V
EE
and the number of enabled
outputs. A simplifying assumption is that one of each (enabled)
differential output pair will be low and draw the full output cur-
rent (and dissipate most of the power for that output), while the
complementary output of the pair will be high and draw insig-
ni
fi
cant current. Thus, its power dissipation of the high output
can be ignored and the output power dissipation for each output
can be assumed to occur in a single static low output that sinks
the full output-programmed current.
The voltage across which this current flows can also vary, depend-
ing on the output circuit design and the supplies that are used
for the data path circuitry. In general, however, there will be a
voltage difference between a logic low signal and V
EE
. This is
the drop across which the output current flows. For a worst
case, this voltage can be as high as 3.5 V. Thus, for all outputs
enabled and the programmed output current set to 25 mA, the
power dissipated by the outputs:
P
= 3.5
V
(25
mA
)
×
17 = 1.49
W
HEAT SINKING
Depending on several factors in its operation, the AD8150 can
dissipate upwards of 2 W or more. The part is designed to oper-
ate without the need for an explicit external heatsink. However,
the package design offers enhanced heat removal via some of the
package pins to the PC board traces.
The V
EE
pins on the input sides of the package (Pins 1 to 46 and
Pins 93 to 138) have
“fi
nger
”
extensions inside the package
that connect to the
“
paddle
”
upon which the IC chip is mounted.
These pins provide a lower thermal resistance from the IC to
the V
EE
pins than other pins that just have a bond wire. As a
result these pins can be used to enhance the heat removal pro-
cess from the IC to the circuit board and ultimately to the ambient.
The V
EE
pins described above should be connected to a large area
of circuit board trace material in order to take most advantage
their lower thermal resistance. If there is a large area available
on an inner layer that is at V
EE
potential, then vias can be pro-
vided from the package pin traces to this layer. There should be
no thermal-relief pattern when connecting the vias to the inner
layers for these V
EE
pins. Additional vias in parallel and close to
the pin leads can provide an even lower thermal resistive path. If
possible to use, 2 oz. copper foil will provide better heat removal
than 1 oz.
The AD8150 package has a speci
fi
ed thermal impedance
θ
JA
of
30
°
C/W. This is the worst case, still-air value that can be expected
when the circuit board does not signi
fi
cantly enhance the heat
removal from the package. By using the concept described above
or by using forced-air circulation, the thermal impedance can be
lowered.
For an extreme worst case analysis, the junction rise above the
ambient can be calculated assuming 2 W of power dissipation
and
θ
JA
of 30
°
C/W to yield a 60
°
C rise above the ambient. There
are many techniques described above that can mitigate this situa-
tion. Most actual circuits will not result in this high a rise of the
junction temperature above the ambient.
APPLICATIONS
AD8150 INPUT AND OUTPUT BUSING
Although the AD8150 is a digital part, in any application that
runs at high speed, analog design details will have to be given very
careful consideration. At high data rates, the design of the signal
channels will have a strong influence on the data integrity and
its associated jitter and ultimately bit error rate (BER).
While it might be considered very helpful to have a suggested cir-
cuit board layout for any particular system con
fi
guration, this is
not something that can be practically realized. Systems come in
all shapes, sizes, speeds, performance criteria and cost constraints.
Therefore, some general design guidelines will be presented
that can be used for all systems and judiciously modi
fi
ed where
appropriate.
High-speed signals travel best, i.e. maintain their integrity, when
they are carried by a uniform transmission line that is properly
terminated at either end. Any abrupt mismatches in impedance
or improper termination will create reflections that will add to
or subtract from parts of the desired signal. Small amounts of
this effect are unavoidable, but too much will distort the signal
to the point that the channel BER will increase. It is dif
fi
cult to
fully quantify these effects, because they are influenced by many
factors in the overall system design.
A constant-impedance transmission line is characterized by
having a uniform cross-section pro
fi
le over its entire length. In
particular, there should be no
“
stubs,
”
which are branches that
intersect the main run of the transmission line. These can have
an electrical
“
appearance
”
that is approximated by a lumped
element, such as a capacitor, or if long enough, as another trans-
mission line. To the extent that stubs are unavoidable in a design,
their effect can be minimized by making them as short as pos-
sible and as high an impedance as possible.
Figure 35 shows a differential transmission line that connects
two differential outputs from AD8150s to a generic receiver. A
more generalized system can have more outputs bused, and
more receivers on the same bus, but all the same concepts apply.
The inputs of the AD8150 can also be considered as a receiver.
The transmission lines that bus all of the devices together are
shown with terminations at each end.
The individual outputs of the AD8150 are stubs that intersect
the main transmission line. Ideally, their current-source outputs
would be in
fi
nite impedance, and they would have no effect on
signals that propagate along the transmission line. In reality, each
相關PDF資料 |
PDF描述 |
|---|---|
| AD8150 | 33 x 17, 1.5 Gbps Digital Crosspoint Switch |
| AD8150AST | 33 x 17, 1.5 Gbps Digital Crosspoint Switch |
| AD8151-EVAL | GPA/SK 300X280X1,5... |
| AD8151 | 33 x 17, 3.2 Gb/s Digital Crosspoint Switch |
| AD8151AST | 33 x 17, 3.2 Gb/s Digital Crosspoint Switch |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD8151 | 制造商:AD 制造商全稱:Analog Devices 功能描述:33 x 17, 3.2 Gb/s Digital Crosspoint Switch |
| AD8151AST | 制造商:AD 制造商全稱:Analog Devices 功能描述:33 x 17, 3.2 Gb/s Digital Crosspoint Switch |
| AD8151ASTZ | 功能描述:IC CROSSPOINT SWIT 33X17 184LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關，多路復用器，多路分解器 系列:XStream™ 其它有關文件:STG4159 View All Specifications 標準包裝:5,000 系列:- 功能:開關 電路:1 x SPDT 導通狀態電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，FCBGA 供應商設備封裝:7-覆晶 包裝:帶卷 (TR) |
| AD8151-EVAL | 制造商:Analog Devices 功能描述:EVAL KIT FOR 33 17, 3.2 GBPS DGTL CROSSPOINT SWIT - Bulk |
| AD8151XSTZ | 功能描述:IC CROSSPOINT SWITCH 制造商:analog devices inc. 系列:* 零件狀態:上次購買時間 標準包裝:1 |
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