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參數資料
| 型號： | AD8178-EVALZ1 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 450 MHz, Triple 16 】 5 Video Crosspoint Switch |
| 中文描述： | 450兆赫，三16】5視頻交叉點開關 |
| 文件頁數： | 32/40頁 |
| 文件大小： | 545K |
| 代理商： | AD8178-EVALZ1 |
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AD8178
At low frequencies, this is a negligible component of crosstalk,
but PSRR falls off as frequency increases. With differential,
balanced loads, as one output draws current from the positive
supply, the other output draws current from the negative supply.
When the phase alternates, the first output draws current from
the negative supply and the second draws from the positive
supply. The effect is that a more constant current is drawn from
each supply, such that the crosstalk-inducing supply fluctuation
is minimized.
A third benefit of driving balanced loads is that the output pulse
response changes as the load changes. The differential signal
control loop in the AD8178 forces the difference of the outputs
to be a fixed ratio to the difference of the inputs. If the two
output responses are different due to loading, this creates a
difference that the control loop sees as signal response error, and
it attempts to correct this error. This distorts the output signal
from the ideal response compared to the case when the two
outputs are balanced.
Decoupling
The signal path of the AD8178 is based on high open-loop gain
amplifiers with negative feedback. Dominant-pole compensation
is used on-chip to stabilize these amplifiers over the range of
expected applied swing and load conditions. To guarantee this
designed stability, proper supply decoupling is necessary with
respect to both the differential control loops and the common-
mode control loops of the signal path. Signal-generated currents
must return to their sources through low impedance paths at all
frequencies in which there is still loop gain (up to 700 MHz at
a minimum).
The signal path compensation capacitors in the AD8178 are
connected to the VNEG supply. At high frequencies, this limits
the power supply rejection ratio (PSRR) from the VNEG supply
to a lower value than that from the VPOS supply. If given a
choice, an application board should be designed such that the
VNEG power is supplied from a low inductance plane, subject
to a least amount of noise.
VOCM_CMENCON and VOCM_CMENCOFF are high speed
common-mode control loops of all output drivers. In the single-
ended output sense, there is no rejection from noise on these
inputs to the outputs. For this reason, care must be taken to
produce low noise sources over the entire range of frequencies
of interest. This is important not only to single-ended operation,
but to differential operation, because there is a common-mode-
to-differential gain conversion that becomes greater at higher
frequencies.
VOCM_CMENCON and VOCM_CMENCOFF are internally
buffered to prevent transients flowing into or out of these inputs
from acting on the source impedance and becoming sources of
crosstalk.
Rev. 0 | Page 32 of 40
Power Dissipation
Calculation of Power Dissipation
10
0
AMBIENT TEMPERATURE (°C)
M
3
4
5
6
7
8
9
15
25
35
45
55
65
75
85
T
J
= 150°C
Figure 50. Maximum Die Power Dissipation vs. Ambient Temperature
The curve in Figure 50 was calculated from
JA
AMBIENT
T
MAX
θ
JUNCTION
MAX
D
T
P
=
,
,
(1)
As an example, if the AD8178 is enclosed in an environment at
45°C (T
A
), the total on-chip dissipation under all load and supply
conditions must not be allowed to exceed 7.0 W.
When calculating on-chip power dissipation, it is necessary to
include the power dissipated in the output devices due to current
flowing in the loads. For a sinusoidal output about ground and
symmetrical split supplies, the on-chip power dissipation due to
the load can be approximated by
P
D,OUTPUT
= (
V
POS
V
OUTPUT,RMS
) ×
I
OUTPUT,RMS
For nonsinusoidal output, the power dissipation should be
calculated by integrating the on-chip voltage drop across the
output devices multiplied by the load current over one period.
The user can subtract the quiescent current for the Class AB
output stage when calculating the loaded power dissipation. For
each output stage driving a load, subtract a quiescent power,
according to
P
DQ,OUTPUT
= (
V
POS
V
NEG
)
×
I
OUTPUT,QUIESCENT
where
I
OUTPUT, QUIESCENT
= 1.65 mA for each single-ended output
pin of the AD8178.
For each disabled RGB output channel, the quiescent power supply
current in V
POS
and V
NEG
drops by approximately 34 mA.
(2)
(3)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD817AN | 功能描述:IC OPAMP HS LP 8-DIP RoHS:否 類別:集成電路 (IC) >> 線性 - 放大器 - 視頻放大器和頻緩沖器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 應用:TFT-LCD 面板：VCOM 驅動器 輸出類型:滿擺幅 電路數:1 -3db帶寬:35MHz 轉換速率:40 V/µs 電流 - 電源:3.7mA 電流 - 輸出 / 通道:1.3A 電壓 - 電源，單路/雙路(±):9 V ~ 20 V，±4.5 V ~ 10 V 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬）裸露焊盤 供應商設備封裝:8-uMax-EP 包裝:管件 |
| AD817AN | 制造商:Analog Devices 功能描述:SEMICONDUCTORSLINEAR |
| AD817ANZ | 功能描述:IC OPAMP HS LP 8-DIP RoHS:是 類別:集成電路 (IC) >> 線性 - 放大器 - 視頻放大器和頻緩沖器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 應用:TFT-LCD 面板：VCOM 驅動器 輸出類型:滿擺幅 電路數:1 -3db帶寬:35MHz 轉換速率:40 V/µs 電流 - 電源:3.7mA 電流 - 輸出 / 通道:1.3A 電壓 - 電源，單路/雙路(±):9 V ~ 20 V，±4.5 V ~ 10 V 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬）裸露焊盤 供應商設備封裝:8-uMax-EP 包裝:管件 |
| AD817AR | 功能描述:IC OPAMP HS LP 8-SOIC RoHS:否 類別:集成電路 (IC) >> 線性 - 放大器 - 視頻放大器和頻緩沖器 系列:- 標準包裝:1,000 系列:- 應用:驅動器 輸出類型:差分 電路數:3 -3db帶寬:350MHz 轉換速率:1000 V/µs 電流 - 電源:14.5mA 電流 - 輸出 / 通道:60mA 電壓 - 電源，單路/雙路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安裝類型:表面貼裝 封裝/外殼:20-VFQFN 裸露焊盤 供應商設備封裝:20-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) |
| AD817AR-EBZ | 功能描述:BOARD EVAL FOR AD817AR RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:* 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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