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參數資料
| 型號： | AD8304ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 160 dB Range (100 pA -10 mA) Logarithmic Converter |
| 中文描述： | LOG OR ANTILOG AMPLIFIER, 10 MHz BAND WIDTH, PDSO14 |
| 封裝： | MO-153AB-1, TSSOP-14 |
| 文件頁數： | 2/20頁 |
| 文件大小： | 4286K |
| 代理商： | AD8304ARU |
REV. A
–2–
AD8304–SPECIFICATIONS
(V
P
= 5 V, V
N
= 0 V, T
A
= 25 C, unless otherwise noted.)
Parameter
Conditions
Min
1
Typ
Max
1
Unit
INPUT INTERFACE
Specified Current Range
Pin 4, INPT; Pin 3 and Pin 5, VSUM
Flows toward INPT Pin
100
pA
mA
V
mV/
°
C
mV
10
0.54
Input Node Voltage
Temperature Drift
Input Guard Offset Voltage
PHOTODIODE BIAS
2
Minimum Value
Transresistance
Internally preset; may be altered
–
40
°
C < T
A
< +85
°
C
V
IN
–
V
SUM
Established between Pin 6, V
PDB
, and Pin 4
I
PD
= 100 pA
0.46
0.5
0.02
–
20
+20
70
100
200
mV
mV/mA
LOGARITHMIC OUTPUT
Slope
Pin 8, VLOG
Laser-trimmed at 25
°
C
0
°
C < T
A
< 70
°
C
Laser-trimmed at 25
°
C
0
°
C < T
A
< 70
°
C
10 nA < I
PD
< 1 mA, Peak Error
1 nA < I
PD
< 1 mA, Peak Error
196
194
60
35
200
204
207
140
175
0.25
0.7
mV/dec
mV/dec
pA
pA
dB
dB
V
V
k
Intercept
100
Law Conformance Error
0.05
0.1
1.6
0.1
5
Maximum Output Voltage
Minimum Output Voltage
Output Resistance
Limited by V
N
= 0 V
Laser-trimmed at 25
°
C
4.95
5.05
REFERENCE OUTPUT
Voltage WRT Ground
Pin 7, VREF
Laser-trimmed at 25
°
C
–
40
°
C < T
A
< +85
°
C
1.98
1.92
2
2.02
2.08
V
V
Output Resistance
2
OUTPUT BUFFER
Input Offset Voltage
Input Bias Current
Incremental Input Resistance
Output Range
Output Resistance
Wide-Band Noise
3
Small Signal Bandwidth
3
Slew Rate
Pin 9, BFIN; Pin 13, BFNG; Pin 11, VOUT
–
20
+20
mV
μ
A
M
V
μ
V/
√
Hz
MHz
V/
μ
s
Flowing out of Pin 9 or Pin 13
0.4
35
V
P
–
0.1
0.5
1
10
15
R
L
= 1 k
to ground
I
PD
> 1
μ
A (see Typical Performance Characteristics)
I
PD
> 1
μ
A (see Typical Performance Characteristics)
0.2 V to 4.8 V output swing
POWER-DOWN INPUT
Logic Level, HI State
Logic Level, LO State
Pin 2, PWDN
–
40
°
C < T
A
< +85
°
C, 2.7 V < V
P
< 5.5 V
–
40
°
C < T
A
< +85
°
C, 2.7 V < V
P
< 5.5 V
Pin 10 and Pin 12, VPS1 and VPS2; Pin 1, VNEG
2
V
V
1
POWER SUPPLY
Positive Supply Voltage
Quiescent Current
In Disabled State
Negative Supply Voltage
4
3.0
5
4.5
60
0
5.5
5.3
V
mA
μ
A
V
|1V
P
–
V
N
| < 8V
–
5.5
NOTES
1
Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.
2
This bias is internally arranged to track the input voltage at
INPT; it is not specified relative to ground.
3
Output Noise and Incremental Bandwidth are functions of Input Current; see Typical Performance Characteristics.
4
Optional
Speci
fi
cations subject to change without notice.
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