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參數資料
型號: AD8313ARM-REEL7
廠商: ANALOG DEVICES INC
元件分類: 模擬信號調理
英文描述: 0.1 GHz-2.5 GHz, 70 dB Logarithmic Detector/Controller
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO8
封裝: MO-187AA, MSOP-8
文件頁數: 9/16頁
文件大小: 261K
代理商: AD8313ARM-REEL7
AD8313
–9–
REV. B
With Pins 7 and 8 disconnected (controller mode), the output
may be stated as
V
OUT
v
V
S
when
V
SLOPE
(P
IN
+
100
) > V
SET
V
OUT
v
0
when
V
SLOPE
(P
IN
+
100
) < V
SET
when the input is stated in terms of the power of a sinusoidal
signal across a net termination impedance of 50
. The transi-
tion zone between high and low states is very narrow, since the
output stage behaves essentially as a fast integrator. The above
equations may be restated as
V
OUT
v
V
S
when
V
SLOPE
log (
V
IN
/2.2
μ
V
) >
V
SET
V
OUT
v
0
when
V
SLOPE
log (
V
IN
/2.2
μ
V
) <
V
SET
A further use of the separate VOUT and VSET pins is in raising
the load-driving current capability by the inclusion of an ex-
ternal NPN emitter follower. More complete information about
usage in these various modes is provided in the Applications
section.
INTERFACES
This section describes the signal and control interfaces and their
behavior. On-chip resistances and capacitances exhibit varia-
tions of up to
±
20%. These resistances are sometimes tempera-
ture dependent and the capacitances may be voltage dependent.
Power-Down Interface, PWDN
The power-down threshold is accurately centered at the midpoint
of the supply as shown in Figure 22. If Pin 5 is left unconnected or
tied to the supply voltage (recommended) the bias enable cur-
rent is shut off, and the current drawn from the supply is pre-
dominately through a nominal 300 k
chain (20
μ
A at 3 V). When
grounded, the bias system is turned on. The threshold level is
accurately at V
POS
/2. The input bias current at the
PWDN pin
when operating in the device “ON” state is approximately
5
μ
A for V
POS
= 3 V.
5
PWDN
VPOS
75k
V
6
COMM
150k
V
50k
V
150k
V
TO BIAS
ENABLE
4
Figure 22. Power-Down Threshold Circuitry
Signal Inputs, INHI, INLO
The simplest low frequency ac model for this interface consists
of just a 900
resistance R
IN
in shunt with a 1.1 pF input ca-
pacitance, C
IN
connected across INHI and
INLO. Figure 23
shows these distributed in the context of a more complete sche-
matic. The input bias voltage shown is for the enabled chip;
when disabled, it will rise by a few hundred millivolts. If the
input is coupled via capacitors, this change may cause a low-
level signal transient to be introduced, having a time-constant
formed by these capacitors and R
IN
. For this reason, large-
valued coupling capacitors should be well matched; this is not
necessary when using the small capacitors found in many im-
pedance transforming networks used at high frequencies.
1.25k
V
COMM
VPOS
INHI
INLO
VPOS
0.5pF
0.5pF
0.7pF
2.5k
V
2.5k
V
~
0.75V
(1ST DETECTOR)
250
V
~
1.4mA
125
V
125
V
1.25k
V
1.24V
GAIN BIAS
TO 2ND
STAGE
TO STAGES
1 THRU 4
1
2
3
4
Figure 23. Input Interface Simplified Schematic
For high frequency use, Figure 24 shows the input impedance
plotted on a Smith chart. This measured result of a typical de-
vice includes a 191 mil 50
trace and a 680 pF capacitor to
ground from the INLO pin.
1.1pF
900
V
1.9GHz
Fr100MHz
1.9GHz
2.5GHz
R
55
22
23
+j X
–j 43
AD8313 MEASURED
2.5GHz
900MHz
100MHz
Figure 24. Typical Input Impedance
Logarithmic/Error Output, VOUT
The rail-to-rail output interface is shown in Figure 25. V
OUT
can run from within about 50 mV of ground, to within about
100 mV of the supply voltage, and is short-circuit safe to either
supply. However, the sourcing load current I
SOURCE
is limited by
that provided by the PNP transistor, to typically 400
μ
A. Larger
load currents can be provided by adding an external NPN tran-
sistor (see Applications). The dc open-loop gain of this amplifier
is high, and it may be regarded essentially as an integrator hav-
ing a capacitance of 2 pF (C
INT
) driven by the current-mode
signals generated by the summed outputs of the nine detector
stages, which is scaled approximately 4.0
μ
A/dB.
COMM
g
m
STAGE
C
INT
LP
LM
10mA
MAX
VOUT
C
L
BIAS
I
SOURCE
400
m
A
VPOS
FROM
SET-POINT
SUMMED
DETECTOR
OUTPUTS
6
8
1
Figure 25. Output Interface Circuitry
Thus, for a midscale RF input of about 3 mV, which is some
40 dB above the minimum detector output, this current is
160
μ
A and the output changes by 8 V/
μ
s. When VOUT is
connected to VSET, the rise and fall times are approximately
40 ns (for R
L
10 k
). The nominal slew rate is
±
2.5 V/
μ
s.
The HF compensation technique results in stable operation with
a large capacitive load, C
L
, though the positive-going slew rate
will then be limited by I
SOURCE
/C
L
to 1 V/
μ
s for C
L
= 400 pF.
相關PDF資料
PDF描述
AD8313ARM 0.1 GHz-2.5 GHz, 70 dB Logarithmic Detector/Controller
AD8313ARM-REEL 0.1 GHz-2.5 GHz, 70 dB Logarithmic Detector/Controller
AD8313-EVAL 0.1 GHz-2.5 GHz, 70 dB Logarithmic Detector/Controller
AD8313 0.1 GHz-2.5 GHz,70dB Logarithmic Detector/Controller(頻率為0.1 GHz-2.5 GHz,增益為70dB的對數檢測器/控制器)
AD8314ARM 100 MHz-2500 MHz 45 dB RF Detector/Controller
相關代理商/技術參數
參數描述
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AD8313ARMZ-REEL7 功能描述:IC LOG DETECTOR/CTRLR 8-MSOP TR RoHS:是 類別:RF/IF 和 RFID >> RF 檢測器 系列:- 產品變化通告:Product Discontinuation 15/May/2006 標準包裝:3,000 系列:- 頻率:100MHz ~ 2GHz RF 型:手機,GSM,DCS,PCS 輸入范圍:- 精確度:- 電源電壓:2.7 V ~ 5.5 V 電流 - 電源:300µA 包裝:帶卷 (TR) 封裝/外殼:SC-74,SOT-457 其它名稱:NCS5000SNT1GOS
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