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參數資料
| 型號： | AD8332-EVAL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Ultralow Noise VGAs with Preamplifier and Programmable RIN |
| 中文描述： | 超低噪聲的VGA前置放大器和可編程與房地產經紀人 |
| 文件頁數： | 25/32頁 |
| 文件大?。?/td> | 482K |
| 代理商： | AD8332-EVAL |
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AD8331/AD8332
Rev. C | Page 25 of 32
G
1m
LO GAIN
MODE
15mV
–4.5
25mV
L
X-AMP
OVERLOAD
POSTAMP
OVERLOAD
X-AMP
OVERLOAD
25mV
POSTAMP
OVERLOAD
4mV
29dB
43.5
INPUT AMPLITUDE (V)
.275
0.1
10m
24.5dB
G
HI GAIN
MODE
7.5
L
41dB
56.5
INPUT AMPLITUDE (V)
24.5dB
1
1m
0.275
0.1
10m
1
0
Figure 72. Overload Gain and Signal Conditions
The previously mentioned clamp interface controls the
maximum output swing of the postamp and its overload
response. When no R
CLMP
resistor is provided, this level defaults
to near 4.5 V p-p differential to protect outputs centered at a
2.5 V common mode. When other common-mode levels are set
through the VCM pin, the value of R
CLMP
should be chosen for
graceful overload. A value of 8.3 k or less is recommended for
1.5 V or 3.5 V common-mode levels (7.2 k for HI gain mode).
This limits the output swing to just above 2 V p-p diff.
OPTIONAL INPUT OVERLOAD PROTECTION.
Applications in which high transients are applied to the LNA
input may benefit from the use of clamp diodes. A pair of back-
to-back Schottky diodes can reduce these transients to
manageable levels. Figure 73 illustrates how such a diode-
protection scheme may be connected.
20
19
4
3
2
LON
VPS
INH
COMM
ENBL
0.1
μ
F
C
SH
FB
C
FB
BAS40-04
R
SH
R
FB
2
3
1
OPTIONAL
SCHOTTKY
OVERLOAD
CLAMP
0
Figure 73. Input Overload Clamping
When selecting overload protection, the important parameters
are forward and reverse voltages and t
rr
(or
τ
rr
.). The Infineon
BAS40 series shown in Figure 73 has a
τ
rr
of 100 ps and V
F
of
310 mV at 1 mA. Many variations of these specifications can be
found in vendor catalogs.
LAYOUT, GROUNDING, AND BYPASSING
Due to their excellent high frequency characteristics, these
devices are sensitive to their PCB environment. Realizing
expected performance requires attention to detail critical to
good high speed board design.
A multilayer board with power and ground plane is
recommended, and unused area in the signal layers should be
filled with ground. The multiple power and ground pins provide
robust power distribution to the device and must all be
connected. The power supply pins should each be with multiple
values of high frequency ceramic chip capacitors to maintain
low impedance paths to ground over a wide frequency range.
These should have capacitance values of 0.01 μF to 0.1 μF in
parallel with 100 pF to 1 nF, and be placed as close as possible to
the pins. The LNA power pins should be decoupled from the
VGA using ferrite beads. Together with the decoupling
capacitors, ferrite beads help eliminate undesired high
frequencies without reducing the headroom, as do small value
resistors.
Several critical LNA areas require special care. The LON and
LOP output traces must be as short as possible before
connecting to the coupling capacitors connected to Pins VIN
and VIP. R
FB
must be placed nearby the LON pin as well.
Resistors must be placed as close as possible to the VGA output
pins VOL and VOH to mitigate loading effects of connecting
traces. Values are discussed in the section entitled Output
Filtering and Series Resistor
Requirements.
Signal traces must be short and direct to avoid parasitic effects.
Wherever there are complementary signals, symmetrical layout
should be employed to maintain waveform balance. PCB traces
should be kept adjacent when running differential signals over a
long distance.
MULTIPLE INPUT MATCHING
Matching of multiple sources with dissimilar impedances can
be accomplished as shown in the circuit of Figure 75. A relay
and low supply voltage analog switch may be used to select
between multiple sources and their associated feedback
resistors. An ADG736 dual SPDT switch is shown in this
example; however, multiple switches are also available and users
are referred to the Analog Devices Selection Guide for switches
and multiplexers.
DISABLING THE LNA
Where accessible, connection of the LNA enable pin to ground
will power down the LNA, resulting in a current reduction of
about half. In this mode, the LNA input and output pins may be
left unconnected, however the power must be connected to all
the supply pins for the disabling circuit to function. Figure 74
illustrates the connections using an AD8331 as an example.
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相關代理商/技術參數 |
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| AD8332-EVALZ | 功能描述:BOARD EVAL FOR AD8332 RoHS:是 類別:編程器，開發系統 >> 評估板 - 運算放大器 系列:X-AMP® 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- |
| AD8333 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DC to 50 MHz, Dual I/Q Demodulator and Phase Shifter |
| AD8333ACPZ | 制造商:Analog Devices 功能描述:I/Q DEMODULATOR DUAL LFCSP-32 制造商:Analog Devices 功能描述:I/Q, DEMODULATOR, DUAL, LFCSP-32 |
| AD8333ACPZ-REEL | 功能描述:IC DEMODULATOR DUAL I/Q 32LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 解調器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 功能:解調器 LO 頻率:- RF 頻率:70MHz ~ 300MHz P1dB:-9dBm 增益:- 噪音數據:6.36dB 電流 - 電源:41.5mA 電源電壓:2.7 V 封裝/外殼:28-WFQFN 裸露焊盤 供應商設備封裝:28-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| AD8333ACPZ-REEL7 | 功能描述:IC DEMODULATOR DUAL I/Q 32LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 解調器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 功能:解調器 LO 頻率:- RF 頻率:70MHz ~ 300MHz P1dB:-9dBm 增益:- 噪音數據:6.36dB 電流 - 電源:41.5mA 電源電壓:2.7 V 封裝/外殼:28-WFQFN 裸露焊盤 供應商設備封裝:28-TQFN-EP（5x5） 包裝:帶卷 (TR) |
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