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參數資料
| 型號： | AD8367-EVAL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | RECTIFIER STANDARD SINGLE 1A 50V 50 30A-ifsm 5uA-ir 1V-vf DO-41 5K/REEL-13 |
| 中文描述： | 500兆赫，線性以dB顯卡帶AGC檢測 |
| 文件頁數： | 9/16頁 |
| 文件大?。?/td> | 607K |
| 代理商： | AD8367-EVAL |
REV. 0
AD8367
–9–
THEORY OF OPERATION
The AD8367 is a variable gain single-ended IF amplifier based
on Analog Devices
’
patented X-AMP architecture. It offers
accurate gain control with a 45 dB span and a 3 dB bandwidth
of 500 MHz. It can be configured as a traditional VGA with
50 dB/V gain scaling or as an AGC amplifier by using the built-
in rms detector. Figure 1 is a simplified block diagram of the
amplifier. The main signal path consists of a voltage-controlled
0 dB to 45 dB variable attenuator followed by a 42.5 dB fixed
gain amplifier. The AD8367 is designed to operate optimally in
a 200
impedance system.
GAIN INTERPOLATOR
g
m
g
m
g
m
g
m
GAIN
INPT
ATTENUATOR LADDER
0dB
–
5dB
–
10dB
–
45dB
INTEGRATOR
OUTPUT
BUFFER
VOUT
200
V
OUT
–
42.5dB
Figure 1. The Simplified Architecture
Input Attenuator and Gain Control
The variable attenuator consists of a 200
single-ended resis-
tive ladder comprising nine 5 dB sections and an interpolator
that selects the attenuation factor. Each tap point down the
ladder network further attenuates the input signal by a fixed
decibel factor. Gain control is achieved by sensing different tap
points with variable transconductance stages. Based on the gain
control voltage, an interpolator selects which stage(s) are active.
For example, if only the first stage is active, the 0 dB tap point is
sensed; if the last stage is active, the 45 dB tap point is sensed.
Attenuation levels that fall between tap points are achieved by
having neighboring g
m
stages active simultaneously, creating a
weighted average of the discrete tap point attenuations. In this
way, a smooth, monotonic attenuation function is synthesized
that is linear-in-dB with a very precise scaling.
The gain of the AD8367 can be an increasing or decreasing
function of the control voltage, V
GAIN
, depending on whether
the MODE pin is pulled up to the positive supply or down to
ground. When the MODE pin is high, the gain increases with
V
GAIN
as shown in Figure 2. The ideal linear-in-dB scaled trans-
fer function is given by,
Gain(dB)
=
×
50
5
V
GAIN
(1)
where
V
GAIN
is expressed in volts. Equation 1 contains the
gain scaling factor of 50 dB/V (20 mV/dB) and the gain intercept
of
–
5 dB which represents the extrapolated gain for V
GAIN
= 0 V.
The gain ranges from
–
2.5 dB to 42.5 dB for V
GAIN
ranging from
50 mV to 950 mV. The deviation from (1), that is, the gain
conformance error, is also illustrated in Figure 2. The ripples in
the error are a result of the interpolation action between tap points.
The AD8367 provides better than
±
0.5 dB of conformance error
over >40 dB gain range at 200 MHz and
±
1 dB at 400 MHz.
V
GAIN
–
V
44
20
–
4
G
–
40
24
16
0
32
28
12
36
8
4
0
1.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
–
0.4
L
–
1.6
0
–
0.8
–
2.4
0.8
0.4
–
1.2
1.2
–
1.6
–
2.0
2.0
LO MODE
HI MODE
50dB/V
GAIN
SLOPE
Figure 2. The gain function can be either an increas-
ing or decreasing function of V
GAIN
depending on the
MODE pin.
The gain is a decreasing function of V
GAIN
when the MODE pin
is low. Figure 2 also illustrates this mode which is described by
Gain (dB)
=
×
45
50
V
GAIN
(2)
This gain mode is required in AGC applications using the built-
in square-law level detector.
Input and Output Interfaces
The AD8367 was designed to operate best in a 200
impedance
system. Its gain range, conformance law, noise and distortion
assume that 200
source and load impedances are used. Interfacing
the AD8367 to other common impedances (from 50
used at
radio frequencies to 1 k
presented by data-converters) can be
accomplished using resistive or reactive passive networks, whose
design depends on specific system requirements such as bandwidth,
return loss, noise figure and absolute gain range.
The input impedance of the AD8367 is nominally 200
, deter-
mined by the resistive ladder network. This presents a 200
dc
resistance to ground, and in cases where an elevated signal poten-
tial is used, ac coupling is necessary. The input signal level must
not exceed 700 mV p-p to avoid overloading the input stage. The
output impedance is determined by an internal 50
damping
resistor, as shown in the simplified schematic in Figure 3.
FROM
INTEGRATOR
V
B1
V
B2
50
V
OUT
Figure 3. A 50
Resistor is Added to the Output to
Prevent Package Resonance
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PDF描述 |
|---|---|
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD8367-EVALZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk 制造商:Analog Devices 功能描述:AD8367 EVALUATION BOARD*NIC* |
| AD8367R703F | 制造商:Analog Devices 功能描述:AEROSPACE 500 MHZ, 45 DB LINEAR-IN-DB VARIABLE GAIN AMPLIFIE - Rail/Tube |
| AD8368 | 制造商:AD 制造商全稱:Analog Devices 功能描述:800 MHz, Linear-in-dB VGA with AGC Detector |
| AD8368_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:800 MHz, Linear-in-dB VGA with AGC Detector |
| AD8368ACP | 制造商:Analog Devices 功能描述:IC AMP VGA AGC 800MHZ 24LFCSP 制造商:Analog Devices 功能描述:IC, AMP, VGA, AGC, 800MHZ, 24LFCSP 制造商:Analog Devices 功能描述:IC, AMP, VGA, AGC, 800MHZ, 24LFCSP; Gain:22dB; Noise Figure Typ:9.5dB; RF IC Case Style:LFCSP; No. of Pins:24; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; RF Type:Cellular; Operating Temperature Min:-40C; Operating Temperature;RoHS Compliant: Yes |
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