
AD8383
Rev. 0 | Page 13 of 16
P
P
P
C
P
PCB
θ
PCB
θ
JC
T
CASE
T
PCB
θ
AIR-PCB
θ
AIR-CASE
T
A
T
J
0
Figure 15. Simplified Thermal Equivalent Circuit
Verification of the Maximum Operating Junction
Temperature
In order to verify the system thermal design for compliance
with the maximum operating junction temperature specifica-
tion, temperature measurements T
CASE
and T
PCB
are required at
the maximum possible total power dissipation in a complete,
fully assembled LCD projection system.
Maximum possible total power dissipation of the AD8383
occurs when the video input to the projector is a pattern with
1-pixel-wide white and black vertical lines. An alternative
pattern that results in the maximum possible total power
dissipation is a 1-pixel checkerboard pattern. The expected total
power dissipation of the AD8383 in a 60 Hz, 6-channel XGA
projector displaying the 1-pixel-wide vertical line or checker-
board pattern is 1.08 W (at AVCC = 15.5 V, VCOM = 7 V, and
LCD capacitance = 150 pF).
Although the case and PCB temperatures are highly dependent
on the PCB design, their measured values are expected to be
similar at approximately 40°C above the ambient (on a typical
PCB with a minimal airflow whose thermal design follows the
recommendations described in this note). The junction temper-
ature then calculates to approximately 10°C above the case and
PCB temperatures. At a 70°C ambient temperature, the junction
temperature is expected to be at approximately 120°C.
The AD8383 has a relatively small thermal mass. In order to
minimize measurement errors due to the thermal mass of the
measuring device, a small-gauge thermocouple or a thermal
probe with a very small thermal mass is required for the mea-
surement of T
CASE
and T
PCB
.
Power-Up and Power-Down Sequencing
As indicated in the Absolute Maximum Ratings, the voltage at
any input pin cannot exceed its supply voltage by more than
0.5 V. To ensure compliance with the Absolute Maximum
Ratings, power-up and power-down sequencing may be
required.
During power-up, initial application of nonzero voltages to any
of the input pins must be delayed until the supply voltage ramps
up to at least the highest maximum operational input voltage.
During power-down, the voltage at any input pin must reach
zero during a period not exceeding the hold-up time of the
power supply.
Failure to comply with the Absolute Maximum Ratings may
result in functional failure or damage to the internal ESD
diodes.
Damaged ESD diodes may cause temporary parametric failures,
which may result in image artifacts. Damaged ESD diodes
cannot provide full ESD protection, thus reducing reliability.
The recommended sequence is
Power ON
1.
Apply power to supplies.
2.
Apply power to other I/Os.
Power OFF
1.
Remove power from I/Os.
2.
VBIAS Generation—V1, V2 Input Pin Functionality
In order to avoid image flicker, a bias voltage of approximately
1 V minimum must be maintained across the pixels of HTPS
LCDs. The AD8383 provides two methods of maintaining this
bias voltage.
Internal Bias Voltage Generation
Standard systems that internally generate the bias voltage
reserve the upper-most code range for the bias voltage and use
the remaining code range to encode the video for gamma
correction.
Remove power from supplies.