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參數資料
| 型號： | AD8555 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Zero-Drift, Digitally Programmable Sensor Signal Amplifier |
| 中文描述： | 零漂移，數字可編程傳感器信號放大器 |
| 文件頁數： | 20/28頁 |
| 文件大小： | 503K |
| 代理商： | AD8555 |
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AD8555
Rev. 0 | Page 20 of 28
0
CODE
0
1
0
0
1
1
WAVEFORM
t
W0
t
WS
t
W0
t
WS
t
WS
t
WS
t
W0
t
WS
t
W1
t
W1
t
W1
Figure 51. Timing Diagram for Code 010011
Table 10. Timing Specifications
Timing Parameter
t
w0
t
w1
t
ws
Description
Pulse Width for Loading 0 into Shift Register
Pulse Width for Loading 1 into Shift Register
Width between Pulses
Specification
Between 50 ns and 10 μs
≥50 μs
≥10 μs
Table 11. 38-Bit Serial Word Format
Field No.
Field 0
Field 1
Field 2
Field 3
Field 4
Field 5
Bits
Bits 0 to 11
Bits 12 to 13
Bits 14 to 15
Bits 16 to 17
Bits 18 to 25
Bits 26 to 37
Description
12-Bit Start of Packet 1000 0000 0001
2-Bit Function
00: Change Sense Current
01: Simulate Parameter Value
10: Program Parameter Value
11: Read Parameter Value
2-Bit Parameter
00: Second Stage Gain Code
01: First Stage Gain Code
10: Output Offset Code
11: Other Functions
2-Bit Dummy 10
8-Bit Value
Parameter 00 (Second Stage Gain Code): 3 LSBs Used
Parameter 01 (First Stage Gain Code): 7 LSBs Used
Parameter 10 (Output Offset Code): All 8 Bits Used
Parameter 11 (Other Functions)
Bit 0 (LSB): Master Fuse
Bit 1: Fuse for Production Test at Analog Devices
Bit 2: Parity Fuse
12-Bit End of Packet 0111 1111 1110
A 38-bit serial word is used, divided into 6 fields. Assuming
each bit can be loaded in 60 μs, the 38-bit serial word transfers
in 2.3 ms. Table 11 summarizes the word format.
Fields 0 and 5 are the start of packet and end of packet field,
respectively. Matching the start of packet field with 1000 0000
0001 and the end of packet field with 0111 1111 1110 ensures
that the serial word is valid and enables decoding of the other
fields. Field 3 breaks up the data and ensures that no data com-
bination can inadvertently trigger the start of packet and end of
packet fields. Field 0 should be written first and Field 5 written
last. Within each field, the MSB must be written first and the
LSB written last. The shift register features power-on reset to
minimize the risk of inadvertent programming; power-on reset
occurs when VDD is between 0.7 V and 2.2 V.
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相關代理商/技術參數 |
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| AD8555_09 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Zero-Drift, Digitally Programmable Sensor Signal Amplifier |
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| AD8555ACP | 制造商:Analog Devices 功能描述:SP AMP CURRENT SENSE AMP SGL R-R I/O 5.5V 16LFCSP EP - Bulk |
| AD8555ACP-R2 | 制造商:Analog Devices 功能描述:SP Amp Current Sense Amp Single R-R I/O 5.5V 16-Pin LFCSP EP T/R 制造商:Rochester Electronics LLC 功能描述:AUTO ZERO AMP W/PROGRAMMABLE GAIN/OFFSET - Bulk |
| AD8555ACP-REEL | 制造商:Analog Devices 功能描述:SP Amp Current Sense Amp Single R-R I/O 5.5V 16-Pin LFCSP EP T/R |
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