- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄373949 > AD8555AR (ANALOG DEVICES INC) Zero-Drift, Digitally Programmable Sensor Signal Amplifier PDF資料下載
參數(shù)資料
| 型號(hào)： | AD8555AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Zero-Drift, Digitally Programmable Sensor Signal Amplifier |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁(yè)數(shù)： | 22/28頁(yè) |
| 文件大小： | 503K |
| 代理商： | AD8555AR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)當(dāng)前第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)
AD8555
Rev. 0 | Page 22 of 28
IN01
IN02
IN03
IN04
IN05
IN06
IN07
IN08
IN09
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IN17
IN18
VA0
VA1
VA2
VB0
VB1
VB2
VB3
VB4
VB5
VB6
VC0
VC1
VC2
VC3
VC4
VC5
VC6
VC7
EOR18
OUT
I0
DOT_SUM
PAR_SUM
PFUSE
MFUSE
IN1
IN2
EOR2
AND2
IN1
IN2
PARITY_ERROR
I1
OUT
I2
OUT
0
Figure 52. Functional Circuit of AD8555 Parity Check
Table 13. Examples of DAT_SUM
Second Stage Gain Code
000
000
000
000
000
001
001
111
First Stage Gain Code
000 0000
000 0000
000 0000
000 0001
100 0001
000 0000
000 0001
111 1111
Output Offset Code
0000 0000
1000 0000
1000 0001
0000 0000
0000 0000
0000 0000
1000 0000
1111 1111
Number of Bits with 1
0
1
2
1
2
1
3
18
DAT_SUM
0
1
0
1
0
1
1
0
VA0 to VA2 is the 3-bit control signal for the second stage gain,
VB0 to VB6 is the 7-bit control signal for the first stage gain,
and VC0 to VC7 is the 8-bit control signal for the output offset.
PFUSE is the signal from the parity fuse, and MFUSE is the
signal from the master fuse.
The function of the 2-input AND gate (cell and2) is to ignore
the output of the parity circuit (signal PAR_SUM) when the
master fuse has not been blown. PARITY_ERROR is set to 0
when MFUSE = 0. In the simulation mode, for example, parity
check is disabled. After the master fuse has been blown, i.e.,
after the AD8555 has been programmed, the output from the
parity circuit (signal PAR_SUM) is fed to PARITY_ERROR.
When PARITY_ERROR is 0, the AD8555 behaves as a pro-
grammed amplifier. When PARITY_ERROR is 1, a parity error
has been detected, and VOUT is connected to VSS.
The 18-bit data signal (VA0 to VA2, VB0 to VB6, and VC0 to
VC7) is fed to an 18-input exclusive-OR gate (Cell EOR18). The
output of Cell EOR18 is the signal DAT_SUM. DAT_SUM = 0 if
there is an even number of 1s in the 18-bit word; DAT_SUM =
1 if there is an odd number of 1s in the 18-bit word. Examples
are given in Table 13.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD8555AR-REEL7 | Zero-Drift, Digitally Programmable Sensor Signal Amplifier |
| AD8555 | Zero-Drift, Digitally Programmable Sensor Signal Amplifier |
| AD8555ACP-R2 | Zero-Drift, Digitally Programmable Sensor Signal Amplifier |
| AD8555ACP-REEL | Zero-Drift, Digitally Programmable Sensor Signal Amplifier |
| AD8561AR | Ultrafast 7 ns Single Supply Comparator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8555AR-EVAL | 制造商:Analog Devices 功能描述:Evaluation Board For Zero-Drift, Digitally Programmable Sensor Signal Amplifier |
| AD8555AR-REEL | 制造商:Analog Devices 功能描述:SP Amp Current Sense Amp Single R-R I/O 5.5V 8-Pin SOIC N T/R |
| AD8555AR-REEL7 | 制造商:Analog Devices 功能描述:SP Amp Current Sense Amp Single R-R I/O 5.5V 8-Pin SOIC N T/R |
| AD8555ARZ | 功能描述:IC AMP CHOPPER 2MHZ 10MA 8SOIC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:DigiTrim® 標(biāo)準(zhǔn)包裝:2,500 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:- 轉(zhuǎn)換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:45nA 電壓 - 輸入偏移:2000µV 電流 - 電源:1.4mA 電流 - 輸出 / 通道:40mA 電壓 - 電源，單路/雙路(±):3 V ~ 32 V，±1.5 V ~ 16 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) 其它名稱:LM324ADTBR2G-NDLM324ADTBR2GOSTR |
| AD8555ARZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Zero-Drift, Digitally Programmable Sensor Signal Amplifier |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。