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參數資料
| 型號： | AD9215BCPZ-105 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 10-Bit, 65/80/105 MSPS, 3V A/D Converter |
| 中文描述： | 1-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC32 |
| 封裝： | MO-220-VHHD-2, LEAD FREE, LFCSP-32 |
| 文件頁數： | 15/36頁 |
| 文件大小： | 1416K |
| 代理商： | AD9215BCPZ-105 |
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AD9215
SNR performance is achieved with the AD9215 set to the largest
input span of 2 V p-p. The relative SNR degradation is 3 dB
when changing from 2 V p-p mode to 1 V p-p mode.
Rev. A | Page 15 of 36
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference volt-
age. The minimum and maximum common-mode input levels
are defined as
VCM
MIN
=
VREF
/2
VCM
MAX
= (
AVDD
+
VREF
)/2
The minimum common-mode input level allows the AD9215 to
accommodate ground-referenced inputs.
Although optimum performance is achieved with a differential
input, a single-ended source may be driven into VIN+ or VIN.
In this configuration, one input accepts the signal, while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal may be
applied to VIN+ while a 1 V reference is applied to VIN. The
AD9215 then accepts a signal varying between 2 V and 0 V. In
the single-ended configuration, distortion performance may
degrade significantly as compared to the differential case. How-
ever, the effect is less noticeable at lower input frequencies.
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9215 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD
/2, and the driver can be configured in a Sallen Key filter
topology to provide band limiting of the input signal.
0
AD8138
AD9215
VIN+
VIN–
AVDD
AGND
1V p-p
R
R
C
C
499
499
499
523
49.9
1k
1k
0.1
μ
F
V
CM
Figure 32. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9215. This is especially true in IF
undersampling applications where frequencies in the 70 MHz to
200 MHz range are being sampled. For these applications, differ-
ential transformer coupling is the recommended input configura-
tion. The value of the shunt capacitor is dependant on the input
frequency and source impedance and should be reduced or re-
moved. An example of this is shown in Figure 33.
0
AD9215
VIN+
VIN–
AVDD
AGND
2Vp-p
R
R
C
C
49.9
0.1
μ
F
AVDD
1k
1k
Figure 33. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a deg-
radation in SFDR and distortion performance due to the large
input common-mode swing. However, if the source impedances
on each input are kept matched, there should be little effect on
SNR performance. Figure 34 details a typical single-ended input
configuration.
0
2V p-p
R
R
C
C
49.9
0.1
μ
F
10
μ
F
10
μ
F
0.1
μ
F
AD9215
VIN+
VIN–
AVDD
AGND
AVDD
1k
1k
1k
1k
Figure 34. Single-Ended Input Configuration
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be sensi-
tive to clock duty cycle. Commonly, a 5% tolerance is required
on the clock duty cycle to maintain dynamic performance char-
acteristics. The AD9215 contains a clock duty cycle stabilizer
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9215. As shown in Figure 25, noise and distortion per-
formance are nearly flat over a 50% range of duty cycle. For best
ac performance, enabling the duty cycle stabilizer is recom-
mended for all applications.
The duty cycle stabilizer uses a delay-locked loop (DLL) to cre-
ate the nonsampling edge. As a result, any changes to the sam-
pling frequency require approximately 100 clock cycles to allow
the DLL to acquire and lock to the new rate.
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相關代理商/技術參數 |
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| AD9215BCPZ-65 | 功能描述:IC ADC 10BIT 65MSPS 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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| AD9215BRU-105EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 65/80/105 MSPS, 3V A/D Converter |
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