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參數資料
型號: AD9225-EB
廠商: Analog Devices, Inc.
英文描述: Complete 12-Bit, 25 MSPS Monolithic A/D Converter
中文描述: 完整的12位,25 MSPS的單片機的A / D轉換器
文件頁數: 15/24頁
文件大小: 321K
代理商: AD9225-EB
AD9225
–15–
REV. A
Figure 24 shows the schematic of the suggested transformer
circuit. The circuit uses a minicircuits RF transformer, model
#T4-1T, which has an impedance ratio of four (turns ratio of
2). The schematic assumes that the signal source has a 50
source impedance. The 1:4 impedance ratio requires the 200
secondary termination for optimum power transfer and VSWR.
The center tap of the transformer provides a convenient means
of level-shifting the input signal to a desired common-mode
voltage.
VINA
VINB
AD9225
200
V
49.9
V
R
S
33
V
CML
MINICIRCUITS
T4-1T
0.1
m
F
R
S
33
V
Figure 24. Transformer Coupled Input
This (Figure 24) configuration was used to gather the differen-
tial data on pages 2 and 3.
Transformers with other turns ratios may also be selected to
optimize the performance of a given application. For example, a
given input signal source or amplifier may realize an improve-
ment in distortion performance at reduced output power levels
and signal swings. For example, selecting a transformer with a
higher impedance ratio (e.g., Minicircuits T16-6T with a 1:16
impedance ratio) effectively “steps up” the signal level thus
further reducing the driving requirements of the signal source.
Referring to Figure 24, a series resistors, R
S
, and shunt capaci-
tor, C
S
, were inserted between the AD9225 and the secondary
of the transformer. The value of 33
was selected to specifi-
cally optimize both the THD and SNR performance of the A/D.
R
S
and C
S
help provide a low-pass filter to block high frequency
noise.
The AD9225 can be easily configured for either a 2 V p-p input
span or 4.0 V p-p input span by setting the internal reference
(see Table II). Other input spans can be realized with two exter-
nal gain setting resistors as shown in Figure 28 of this data
sheet. Figures 25a and 25b demonstrate how both spans of the
AD9225 achieve the high degree of linearity and SFDR over a
wide range of amplitudes required by the most demanding com-
munication applications.
Figures 25a and 25b demonstrate the flexibility of common-
mode voltage (transformer center tap) with respect to THD.
COMMON-MODE VOLTAGE – V
–76
–78
–86
–80
–82
–84
0
5
1
T
2
3
4
F
IN
= 10MHz
F
IN
= 2.5MHz
Figure 25a. Common-Mode Voltage vs. THD
(A
IN
= 2 V Differential)
COMMON-MODE VOLTAGE – V
–76
–78
–86
–80
–82
–84
0.5
1.0
T
1.5
F
IN
= 10MHz
F
IN
= 2.5MHz
2.0
2.5
3.0
3.5
4.0
4.5
Figure 25b. Common-Mode Voltage vs. THD
(A
IN
= 4 V Differential)
FUND
2ND
3RD
4TH
–119.7
–110.0
–100.0
–90.0
–80.0
–70.0
–60.0
–50.0
–40.0
–30.0
–20.0
–10.0
0.0
2.0E+6
4.0E+6
6.0E+6
8.0E+6
10.0E+6
12.5E+6
F
IN
= 2.5MHz
F
S
= 25MHz
Figure 25c. Single Tone Frequency Domain Plot
Common-Mode Voltage = 2.5 V (A
IN
= 4 V
Differential)
相關PDF資料
PDF描述
AD9225AR Complete 12-Bit, 25 MSPS Monolithic A/D Converter
AD9225ARS Complete 12-Bit, 25 MSPS Monolithic A/D Converter
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相關代理商/技術參數
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