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參數資料
| 型號： | AD9225-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit, 25 MSPS Monolithic A/D Converter |
| 中文描述： | 完整的12位，25 MSPS的單片機的A / D轉換器 |
| 文件頁數： | 20/24頁 |
| 文件大小： | 321K |
| 代理商： | AD9225-EB |
AD9225
–20–
REV. A
A
IN
– dBFS
90
95
–15
0
S
–10
–5
85
70
55
50
100
80
75
65
60
SFDR
DUAL-TONE
(dBFS)
SNR
SINGLE-TONE
(dBc)
SFDR
SINGLE-TONE
(dBFS)
Figure 38. IF Undersampling at 70 MHz (F
1
= 69.50 MHz,
F
2
= 70.11 MHz, CLOCK = 25 MHz)
A
IN
– dBFS
90
95
–15
0
S
–10
–5
85
70
55
50
100
80
75
65
60
SFDR
DUAL-TONE
(dBFS)
SNR
SINGLE-TONE
(dBc)
SFDR
SINGLE-TONE
(dBFS)
Figure 39. IF Undersampling at 85 MHz (F
1
= 84.81 MHz,
F
2
= 85.23 MHz, CLOCK = 20 MHz)
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power
plane, PCB insulation and ground plane.
These characteristics result in both a reduction of electromag-
netic interference (EMI) and an overall improvement in
performance.
It is important to design a layout that prevents noise from cou-
pling onto the input signal. Digital signals should not be run in
parallel with input signal traces and should be routed away from
the input circuitry. While the AD9225 features separate analog
and driver ground pins, it should be treated as an analog com-
ponent. The AVSS and DRVSS pins must be joined together
directly under the AD9225. A solid ground plane under the A/D
is acceptable if the power and ground return currents are care-
fully managed. Alternatively, the ground plane under the A/D
may contain serrations to steer currents in predictable directions
where cross coupling between analog and digital would other-
wise be unavoidable. The AD9225/AD9225EB ground layout,
shown in Figure 47, depicts the serrated type of arrangement.
The board is primarily built over a common ground plane. It has a
“slit” to route currents near the clock driver. Figure 40 illustrates
a general scheme of ground and power implementation, in and
around the AD9225.
ANALOG
CIRCUITS
DIGITAL
LOGIC
ICs
D
V
A
A
D
DVSS
AVSS
A
B
I
A
I
D
AVDD
DVDD
LOGIC
SUPPLY
D
A
V
IN
C
STRAY
C
STRAY
GND
A
= ANALOG
D
= DIGITAL
ADC
IC
DIGITAL
CIRCUITS
A
A
Figure 40. Ground and Power Consideration
Analog and Digital Driver Supply Decoupling
The AD9225 features separate analog and driver supply and
ground pins, helping to minimize digital corruption of sensitive
analog signals. In general, AVDD, the analog supply, should be
decoupled to AVSS, the analog common, as close to the chip as
physically possible. Figure 41 shows the recommended decou-
pling for the analog supplies; 0.1
μ
F ceramic chip and 10
μ
F
tantalum capacitors should provide adequately low impedance
over a wide frequency range. Note that the AVDD and AVSS
pins are co-located on the AD9225 to simplify the layout of the
decoupling capacitors and provide the shortest possible PCB
trace lengths. The AD9225/AD9225EB power plane layout,
shown in Figure 48 depicts a typical arrangement using a multi-
layer PCB.
0.1
m
F
AVDD
AVSS
AD9225
10
m
F
Figure 41. Analog Supply Decoupling
The CML is an internal analog bias point used internally by the
AD9225. This pin must be decoupled with at least a 0.1
μ
F
capacitor as shown in Figure 42. The dc level of CML is ap-
proximately AVDD/2. This voltage should be buffered if it is to
be used for any external biasing.
0.1
m
F
CML
AD9225
Figure 42. CML Decoupling
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