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參數資料
| 型號： | AD9236BRUZRL7-80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 80 MSPS, 3V A/D Converter |
| 中文描述： | 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | LEAD FREE, MO-153AE, TSSOP-28 |
| 文件頁數： | 14/36頁 |
| 文件大小： | 2056K |
| 代理商： | AD9236BRUZRL7-80 |
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AD9236
THEORY OF OPERATION
The AD9236 architecture consists of a front-end sample-and-
hold amplifier (SHA) followed by a pipelined switched capaci-
tor ADC. The pipelined ADC is divided into three sections,
consisting of a 4-bit first stage followed by eight 1.5-bit stages
and a final 3-bit flash. Each stage provides sufficient overlap to
correct for flash errors in the preceding stages. The quantized
outputs from each stage are combined into a final 12-bit result
in the digital correction logic. The pipelined architecture per-
mits the first stage to operate on a new input sample, while the
remaining stages operate on preceding samples. Sampling
occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output-
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT AND REFERENCE OVERVIEW
The analog input to the AD9236 is a differential switched
capacitor SHA that has been designed for optimum perform-
ance while processing a differential input signal. The SHA input
can support a wide common-mode range (VCM) and maintain
excellent performance, as shown in
mon-mode voltage of midsupply minimizes signal-dependant
errors and provides optimum performance.
. An input com-
Figure 26
Figure 26. SNR, SFDR vs. Common-Mode Level
100
S
50
55
60
65
70
75
80
85
90
95
0.5
1.0
1.5
2.0
2.5
3.0
COMMON-MODE LEVEL (V)
03066-0-016
SFDR (2.5MHz)
SFDR (39MHz)
SNR (2.5MHz)
SNR (39MHz)
Referring to F
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s
input; therefore, the precise values are dependant upon the
application. In IF undersampling applications, any shunt capaci-
tors should be reduced or removed. In combination with the
driving source impedance, they would limit the input
bandwidth.
, the clock signal alternately switches the
igure 27
Figure 27. Switched-Capacitor SHA Input
03066-0-012
H
H
VIN+
VIN–
C
PAR
C
PAR
T
T
5pF
5pF
T
T
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages,
REFT
and
REFB
, that define the
span of the ADC core. The output common mode of the refer-
ence buffer is set to midsupply, and the
REFT
and
REFB
volt-
ages and span are defined as follows:
(
)
(
(
)
)
VREF
REFB
REFT
Span
VREF
AVDD
REFB
VREF
AVDD
REFT
×
=
×
=
=
+
=
2
2
2
1
2
1
It can be seen from the equations above that the
REFT
and
REFB
voltages are symmetrical about the midsupply voltage and, by defi-
nition, the input span is twice the value of the
VREF
voltage.
The internal voltage reference can be pin strapped to fixed val-
ues of 0.5 V or 1.0 V, or adjusted within the same range as dis-
cussed in the
SNR performance is achieved with the AD9236 set to the largest
section. Maximum
Internal Reference Connection
Rev. A | Page 14 of 36
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| AD9237BCPZ-20 | 功能描述:IC ADC 12BIT SGL 20MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
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