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參數資料
| 型號： | AD9240 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 14-Bit, 10 MSPS Monolithic A/D Converter |
| 中文描述： | 完整的14位，10 MSPS的單片機的A / D轉換器 |
| 文件頁數： | 19/24頁 |
| 文件大小： | 328K |
| 代理商： | AD9240 |
AD9240
REV. A
–19–
Table V. Out-of-Range Truth Table
OTR
MSB
Analog Input Is
0
0
1
1
0
1
0
1
In Range
In Range
Underrange
Overrange
OVER = “1”
UNDER = “1”
MSB
OTR
MSB
Figure 46. Overrange or Underrange Logic
Digital Output Driver Considerations (DRVDD)
The AD9240 output drivers can be configured to interface with
+5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V
respectively. The AD9240 output drivers are sized to provide
sufficient output current to drive a wide variety of logic families;
large drive currents tend to cause glitches on the supplies and may
affect SINAD performance. Applications requiring the AD9240 to
drive large capacitive loads or large fanout may require additional
decoupling capacitors on DRVDD. In extreme cases, external
buffers or latches may be required.
Clock Input and Considerations
The AD9240 internal timing uses the two edges of the clock
input to generate a variety of internal timing signals. The clock
input must meet or exceed the minimum specified pulsewidth
high and low (t
CH
and t
CL
) specifications for the given A/D, as
defined in the Switching Specifications at the beginning of the
data sheet, to meet the rated performance specifications. For
example, the clock input to the AD9240 operating at 10 MSPS
may have a duty cycle between 45% to 55% to meet this timing
requirement since the minimum specified t
CH
and t
CL
is 45 ns.
For clock rates below 10 MSPS, the duty cycle may deviate
from this range to the extent that both t
CH
and t
CL
are satisfied.
All high speed high resolution A/Ds are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (f
IN
), due only to aperture jitter (t
A
), can be
calculated with the following equation:
SNR
= 20 log
10
[1/(2
π
f
IN
t
A
)
]
In the equation, the rms aperture jitter, t
A
, represents the root-
sum square of all the jitter sources, which include the clock
input, analog input signal and A/D aperture jitter specification.
For example, if a 5.0 MHz full-scale sine wave is sampled by an
A/D with a total rms jitter of 15 ps, the SNR performance of the
A/D will be limited to 66.5 dB. Undersampling applications are
particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9240. As such, supplies for clock drivers should be separated
from the A/D output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter crystal controlled oscil-
lators make the best clock sources. If the clock is generated from
another type of source (by gating, dividing or other method), it
should be retimed by the original clock at the last step.
Most of the power dissipated by the AD9240 is from the analog
power supply; however, lower clock speeds will reduce digital
current slightly. Figure 47 shows the relationship between power
and clock rate.
CLOCK FREQUENCY – MHz
400
2002
20
4
6
8
10
12
14
16
18
380
300
260
240
220
360
340
280
320
P
Figure 47. Power Consumption vs. Clock Frequency
(R
BIAS
= 2 k
)
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power
plane, PCB insulation and ground plane.
These characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in
performance.
It is important to design a layout that prevents noise from coupling
onto the input signal. Digital signals should not be run in paral-
lel with input signal traces and should be routed away from the
input circuitry. While the AD9240 features separate analog and
digital ground pins, it should be treated as an analog component.
The AVSS, DVSS and DRVSS pins must be joined together
directly under the AD9240. A solid ground plane under the A/D
is acceptable if the power and ground return currents are care-
fully managed. Alternatively, the ground plane under the A/D
may contain serrations to
steer
currents in predictable directions
where cross-coupling between analog and digital would other-
wise be unavoidable. The AD9240/EB ground layout, shown in
Figure
57, depicts the serrated type of arrangement. The analog
and digital grounds are connected by a jumper below the A/D.
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