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參數資料
| 型號： | AD9445-BB-PCB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit, 105/125 MSPS, IF Sampling ADC |
| 中文描述： | 14位，一百二十五分之一百○五MSPS的，中頻采樣ADC |
| 文件頁數： | 24/40頁 |
| 文件大小： | 965K |
| 代理商： | AD9445-BB-PCB |
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AD9445
THEORY OF OPERATION
The AD9445 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated, high bandwidth
track-and-hold circuit that samples the signal prior to quantization
by the 14-bit pipeline ADC core. The device includes an on-board
reference and input logic that accepts TTL, CMOS, or LVPECL
levels. The digital output logic levels are user selectable as standard
3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT
MODE pin.
Rev. 0 | Page 24 of 40
ANALOG INPUT AND REFERENCE OVERVIEW
A stable and accurate 0.5 V band gap voltage reference is built
into the AD9445. The input range can be adjusted by varying
the reference voltage applied to the AD9445, using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly.
Internal Reference Connection
A comparator within the AD9445 detects the potential at the
SENSE pin and configures the reference into three possible states,
which are summarized in Table 9. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 59), setting VREF
to ~1.0 V. Connecting the
SENSE pin to VREF switches the reference amplifier output to
the SENSE pin, completing the loop and providing a ~1.0 V
reference output. If a resistor divider is connected as shown in
Figure 60, the switch again sets to the SENSE pin. This puts the
reference amplifier in a noninverting mode with the VREF
output defined as
1
×
=
R1
R2
V
VREF
5
In all reference configurations, REFT and REFB drive the
analog-to-digital conversion core and establish its input span.
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
Internal Reference Trim
The internal reference voltage is trimmed during the production
test to adjust the gain (analog input voltage range) of the AD9445.
Therefore, there is little advantage to the user supplying an external
voltage reference to the AD9445. The gain trim is performed
with the AD9445 input range set to 2.0 V p-p nominal (SENSE
Table 9. Reference Configuration Summary
Selected Mode
External Reference
Programmable Reference
connected to AGND). Because of this trim and the maximum ac
performance provided by the 2.0 V p-p analog input range, there
is little benefit to using analog input ranges <2 V p-p. Users are
cautioned that the differential nonlinearity of the ADC varies
with the reference voltage. Configurations that use <2.0 V p-p
may exhibit missing codes and, therefore, degraded noise and
distortion performance.
10
μ
F+
0.1
μ
F
VREF
SENSE
0.5V
AD9445
VIN–
VIN+
REFT
0.1
μ
F
0.1
μ
F
10
μ
F
0.1
μ
F
REFB
SELECT
LOGIC
ADC
CORE
+
0
Figure 59. Internal Reference Configuration
0
10
μ
F+
0.1
μ
F
VREF
SENSE
R2
R1
0.5V
AD9445
VIN–
VIN+
REFT
0.1
μ
F
0.1
μ
F
10
μ
F
0.1
μ
F
REFB
SELECT
LOGIC
ADC
CORE
+
Figure 60. Programmable Reference Configuration
SENSE Voltage
AVDD1
0.2 V to VREF
Resulting VREF (V)
N/A
+
×
R1
1.0
Resulting Differential Span (V p-p)
2 × external reference
2 × VREF
R2
0.5
(See Figure 60)
Internal Fixed Reference
AGND to 0.2 V
2.0
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相關代理商/技術參數 |
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| AD9445BSV-105 | 制造商:Analog Devices 功能描述:ADC SGL PIPELINED 105MSPS 14BIT PARALLEL 100TQFP EP - Bulk |
| AD9445BSVZ-105 | 功能描述:IC ADC 14BIT 105MSPS 100-TQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
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| AD9445-IF-LVDS | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 105/125 MSPS, IF Sampling ADC |
| AD9445-IF-LVDS/PCB | 制造商:Analog Devices 功能描述:Evaluation Kit For 14-Bit, 105/125 MAPA, IF Sampling ADC 制造商:Analog Devices 功能描述:EVAL KIT FOR 14BIT, 105/125 MSPS, IF SAMPLING ADC - Bulk |
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