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參數資料
| 型號： | AD9661A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Laser Diode Driver with Light Power Control(帶光功率控制的激光二極管驅動器) |
| 中文描述： | 激光二極管驅動器，帶有光功率控制（帶光功率控制的激光二極管驅動器） |
| 文件頁數： | 7/12頁 |
| 文件大?。?/td> | 184K |
| 代理商： | AD9661A |
AD9661A
REV. 0
–7–
TIME CONSTANTS –
t
100
30
00
5
1
%
2
4
20
10
3
40
50
60
70
80
90
Figure 4. Calibration Time
Initial calibration
is required after power-up or any other time
the laser has been disabled. Disabling the AD9661A drives the
hold capacitor to
≈
V
REF
. In this case, or in any case where the
output current is more than 10% out of calibration, R will range
from 300
to 550
for the model above; the higher value should
be used for calculating the worst case calibration time. Following
the example above, if C
HOL D
were chosen as 4.5 nF, then
τ
= RC = 550
×
4.5 nF would be 2.48
μ
s. For an initial
calibration error < 1%, the initial calibration time should be
> 5
τ
= 12.36
μ
s.
Initial calibration time will actually be better than this calcula-
tion indicates, as a significant portion of the calibration time will
be within 10% of the final value, and the output resistance in
the AD9660’s T /H decreases as the hold voltage approaches its
final value.
Recalibration
is functionally identical to initial calibration, but
the loop need only correct for droop. Because droop is assumed
to be a small percentage of the initial calibration (< 10%), the
resistance for the model above will be in the range of 75
to
140
. Again, the higher value should be used to estimate the
worst case time needed for recalibration.
Continuing with the example above, since the droop error dur-
ing hold time is < 5%, we meet the criteria for recalibration and
τ
= RC = 140
×
4.5 nF = 0.64
μ
s. T o get a final error of 1%
after recalibration, the 5% droop must be corrected to within a
20% error (20%
×
5% = 1%). A 2
τ
recalibration time of 1.2
μ
s
is sufficient.
Continuous Recalibration
In applications where the hold capacitor is small (< 500 pF) and
the WRIT E PULSE signals always have a pulse width > 25 ns,
the user may continuously calibrate the feedback loop. In such
an application, the
CAL
signal should be held logic LOW, and
the PULSE signal will control loop calibration via the internal
AND gate. In such application, it is important to optimize the
layout for the T ZA (POWER MONIT OR, GAIN, R
GAIN
and
C
GAIN
).
Driving the Analog Inputs
T he POWER LEVEL input of the AD9661A drives the track
and hold amplifier and allows the user to adjust the amount of
output current as described above. T he input voltage range is
V
REF
to V
REF
+ 1.6 V, requiring the user to create an offset of
V
REF
for a ground based signal (see below for description of the
on board level shift circuit). T he circuit below will perform the
level shift and scale the output of a DAC whose output is from
ground to a positive voltage. T his solution is especially attrac-
tive because both the DAC and the op amp can run off a single
+5 V supply, and the op amp doesn’t have to swing rail to rail.
DAC
V
DAC
OP191
+5V
V
REF
+
V
DAC
R2
POWER LEVEL
BIAS LEVEL
V
REF
AD9661A
R1
R1
R2
R2
Figure 5. Driving the Analog Inputs
Using the Level Shift Circuit
T he AD9661A includes an on board level shift circuit to provide
the offset described above. T he input, LEVEL SHIFT IN, has
an input range from 0.1 V to 1.6 V. T he output, LEVEL
SHIFT OUT , has a range from V
REF
to V
REF
+1.6 V, and can
drive POWER MONIT OR. T he linearity of the level shift cir-
cuit is poor for inputs below 100 mV. Between 100 mV and
1.6 V it is about 7 bits accurate.
Layout Considerations
As in all high speed applications, proper layout is critical; it is
particularly important when both analog and digital signals are
involved. Analog signal paths should be kept as short as
possible, and isolated from digital signals to avoid coupling in
noise. In particular, digital lines should be isolated from
OUT PUT , SENSE IN, POWER LEVEL, LEVEL SHIFT IN
POWER MONIT OR, and HOLD traces. Digital signal paths
should also be kept short, and run lengths matched to avoid
propagation delay mismatch.
Layout of the ground and power supply circuits is also critical.
A single, low impedance ground plane will reduce noise on the
circuit ground. Power supplies should be capacitively coupled
to the ground plane to reduce noise in the circuit. 0.1
μ
F
surface mount capacitors, placed as close as possible to the
AD9661A +V
S
connections, and the +V
S
connection to the laser
diode meet this requirement. Multilayer circuit boards allow
designers to lay out signal traces without interrupting the ground
plane, and provide low impedance power planes to further
reduce noise.
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| AD9662ARQZ-REEL7 | 功能描述:IC LASER DIODE DRIVER 3CH 16QSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 激光驅動器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:60 系列:- 類型:激光二極管驅動器 數據速率:- 通道數:4 電源電壓:3.3V 電流 - 電源:- 電流 - 調制:- 電流 - 偏置:- 工作溫度:0°C ~ 70°C 封裝/外殼:40-TQFN 裸露焊盤 供應商設備封裝:40-TQFN EP 包裝:托盤 安裝類型:表面貼裝 |
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