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參數(shù)資料
| 型號： | AD9833 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | +2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS |
| 中文描述： | 2.5 V至5.5 V，25 MHz低功耗CMOS完整的DDS |
| 文件頁數(shù)： | 16/18頁 |
| 文件大小： | 210K |
| 代理商： | AD9833 |
AD9833
–
16
–
REV PrG
PRELIMINARY TECHNICAL DATA
SCK idles high between write operations (CPOL = 0)
data is valid on the SCK falling edge (CPHA = 1).
When data is being transmitted to the AD9833, the
FSYNC line is taken low (PC7). Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only 8
falling clock edges occuring in the transmit cycle. Data is
transmitted MSB first. In order to load data into the
AD9833, PC7 is held low after the first 8 bits are trans-
ferred and a second serial write operation is performed to
the AD9833. Only after the second 8 bits have been trans-
ferred should FSYNC be taken high again.
68HC11/68L11*
AD9833*
PC7
MOSI
SCK
SDATA
SCLK
FSYNC
* ADDITIONAL PINS OMITTED FOR CLARITY
Figure 10. 68HC11/68L11 to AD9833 Interface
AD9833 to 80C51/80L51 Interface
Figure 11 shows the serial interface between the AD9833
and the 80C51/80L51 microcontroller. The
microcontroller is operated in mode 0 so that TXD of the
80C51/80L51 drives SCLK of the AD9833 while RXD
drives the serial data line SDATA. The FSYNC signal is
again derived from a bit programmable pin on the port
(P3.3 being used in the diagram). When data is to be
transmitted to the AD9833, P3.3 is taken low. The
80C51/80L51 transmits data in 8 bit bytes thus, only 8
falling SCLK edges occur in each cycle. To load the re-
maining 8 bits to the AD9833, P3.3 is held low after the
first 8 bits have been transmitted and a second write op-
eration is initiated to transmit the second byte of data.
P3.3 is taken high following the completion of the second
write operation. SCLK should idle high between the two
write operations. The 80C51/80L51 outputs the serial
data in a format which has the LSB first. The AD9833
accepts the MSB first (the 4 MSBs being the control in-
formation, the next 4 bits being the address while the 8
LSBs contain the data when writing to a destination regis-
ter). Therefore, the transmit routine of the 80C51/80L51
must take this into account and re-arrange the bits so that
the MSB is output first.
80C51/80L51*
AD9833*
P3.3
RXD
TXD
SDATA
SCLK
FSYNC
* ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. 80C51/80L51 to AD9833 Interface
AD9833 to DSP56002 Interface
Figure 12 shows the interface between the AD9833 and
the DSP56002. The DSP56002 is configured for normal
mode asynchronous operation with a Gated internal clock
(SYN = 0, GCK = 1, SCKD = 1). The frame sync pin is
generated internally (SC2 = 1), the transfers are 16 bits
wide (WL1 = 1, WL0 = 0) and the frame sync signal will
frame the 16 bits (FSL = 0). The frame sync signal is
available on pin SC2 but, it needs to be inverted before
being applied to the AD9833. The interface to the
DSP56000/DSP56001 is similar to that of the DSP56002.
DSP56002*
AD9833*
SC2
STD
SCK
SDATA
SCLK
FSYNC
* ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. AD9833 to DSP56002 Interface
AD9833 EVALUATION BOARD
The AD9833 Evaluation Board allows designers to evalu-
ate the high performance AD9833 DDS modulator with
minimum of effort.
To prove that this device will meet the user's waveform
synthesis requirements, the user only require's a power-
supply, an IBM-compatible PC and a spectrum analyser
along with the evaluation board.
The DDS evaluation kit includes a populated, tested
AD9833 printed circuit board. The evaluation board in-
terfaces to the parallel port of an IBM compatible PC.
Software is available with the evaluation board which al-
lows the user to easily program the AD9833. A schematic
of the Evaluation board is shown in Figure 13. The soft-
ware will run on any IBM compatible PC which has
Microsoft Windows95, Windows98 or Windows ME 2000
NT installed.
Using the AD9833 Evaluation Board
The AD9833 Evaluation kit is a test system designed to
simplify the evaluation of the AD9833. An application
note is also available with the evaluation board and gives
full information on operating the evaluation board.
Prototyping Area
An area is available on the evaluation board for the user to
add additional circuits to the evaluation test set. Users
may want to build custom analog filters for the output or
add buffers and operational amplifiers to be used in the
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9833BRM | 功能描述:IC WAVEFORM GEN PROG 10-MSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9833BRM-REEL | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 25MHz 1-DAC 10-Bit Serial 10-Pin MSOP T/R 制造商:Analog Devices 功能描述:PROGRAMMABLE WAVEFORM GENERATOR 10MSOP - Tape and Reel |
| AD9833BRM-REEL7 | 功能描述:IC WAVEFORM GEN PROG 10-MSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9833BRMZ | 功能描述:IC WAVEFORM GENERTR PROG 10-MSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9833BRMZ | 制造商:Analog Devices 功能描述:WAVEFORM GENERATOR 9833 MSOP10 |
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