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參數(shù)資料
型號: AD9833
廠商: Analog Devices, Inc.
英文描述: +2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS
中文描述: 2.5 V至5.5 V,25 MHz低功耗CMOS完整的DDS
文件頁數(shù): 4/18頁
文件大?。?/td> 210K
代理商: AD9833
AD9833
–4–
REV PrG
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AGND to DGND. . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
CAP/2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75 V
Digital I/O Voltage to DGND . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to AGND . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . .–65°C to +150°C
PIN CONFIGURATION
Maximum Junction Temperature . . . . . . . . . . . . . . 150°C
μ
SOIC Package
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . .206°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . .44°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . 300°C
IR Reflow, Peak Temperature . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9833BRM
EVAL-AD9833EB
–40°C to +85°C
14-Pin
μ
SOIC (
Micro Small Outline IC
)
Evaluation Board
RM-10
1
2
3
4
5
6
7
8
TOP VIEW
(Not to Scale)
VDD
CAP/2.5V
DGND
MCLK
VOUT
AGND
FSYNC
SCLK
SDATA
AD9833
10
9
COMP
PIN DESCRIPTION
Pin #
Mnemonic
Function
POWER SUPPLY
2
VDD
Positive power supply for the analog section and the digital interface sections. The on board 2.5 V
regulator is also supplied from VDD. VDD can have a value from +2.3 V to +5.5 V. A 0.1 μF and
10 μF decoupling capacitor should be connected between VDD and AGND.
The digital circuitry operates from a +2.5 V power supply. This +2.5 V is generated from VDD
using an on board regulator (when VDD exceeds +2.7 V). The regulator requires a decoupling
capacitor of typically 100 nF, which is connected from CAP/2.5V to DGND. If VDD is equal to
or less than +2.7 V, CAP/2.5V should be tied directly to VDD.
Digital Ground.
Analog Ground.
ANALOG SIGNAL AND REFERENCE
1
COMP
A DAC Bias Pin. This pin is used for de-coupling the DAC bias voltage.
10
VOUT
Voltage Output. The analog and digital output from the AD9833 is available at this pin. An
external load resistor is not required as the device has a 200W resistor on board.
DIGITAL INTERFACE AND CONTROL
5
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of
MCLK. The output frequency accuracy and phase noise are determined by this clock.
6
SDATA
Serial Data Input. The 16-bit serial data word is applied to this input.
7
SCLK
Serial Clock Input. Data is clocked into the AD9833 on each falling SCLK edge.
8
FSYNC
Active Low Control Input. This is the frame synchronisation signal for the input data. When
FSYNC is taken low, the internal logic is informed that a new word is being loaded into the
device.
3
CAP/2.5V
4
9
DGND
AGND
相關PDF資料
PDF描述
AD9833BRM +2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS
AD9834 Low Power, +2.3 V to +5.5 V, 50 MHz Complete DDS
AD9834BRU Low Power, +2.3 V to +5.5 V, 50 MHz Complete DDS
AD9835 50 MHz CMOS Complete DDS
AD9835BRU 50 MHz CMOS Complete DDS
相關代理商/技術(shù)參數(shù)
參數(shù)描述
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AD9833BRM-REEL7 功能描述:IC WAVEFORM GEN PROG 10-MSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率(位):10 b 主 fclk:25MHz 調(diào)節(jié)字寬(位):32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
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